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Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels | IEEE Journals & Magazine | IEEE Xplore

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels


Abstract:

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is propo...Show More

Abstract:

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.
Published in: IEEE Transactions on Nanotechnology ( Volume: 5, Issue: 3, May 2006)
Page(s): 167 - 173
Date of Publication: 15 May 2006

ISSN Information:


I. Introduction

A SINGLE-ELECTRON transistor (SET) [1] is a promising candidate for ultralow-power and ultrahigh-density circuit systems in the future. In addition, unique features of SETs have been applied to many functional logic circuits [2]–[4]. In order to take full advantage of these unique features in practical circuit applications, a compact and accurate analytical model rather than numerical simulators [5]–[7] is required. Recently, some physically based analytical SET models have been developed for SET circuit simulations with a view to combining with CMOS technology [8]–[12]. However, they do not consider discreteness of the quantum energy levels in the ultrasmall silicon quantum dot of an SET.

References

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