I. Introduction
As the cycle time of computer systems falls into the subnanosecond regime, the fraction of cycle time to accommodate the clock skew for the synchronization of clock signal among the logic gates has risen. While several approaches have been proposed to minimize the clock skew, the delay lines are usually employed in the critical nets of a printed circuit board (PCB), for example, the serpentine or flat spiral routing schemes, as depicted in Fig. 1. Intuitively, the total time delay should be proportional to the total length of the delay line. However, the crosstalk noise induced by those closely packed transmission-line sections may cause a drastic deterioration in the total time delay and even result in the false switching of logic gates, especially for the serpentine delay line [1], [2].
Two typical routing schemes for the delay line. (a) Serpentine routing scheme. (b) Flat spiral routing scheme.