Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology

Accurate measurement and analysis of interconnect capacitance is a critical component of nanometer technology verification. The charged-based capacitance measurement (CBCM) technique has been widely adopted as a robust technique to measure on-chip capacitance test structures. In this paper we present two design improvements for CBCM. The first is an area reduction by using bused circuit architecture to reduce probe pad area required for the test structure input and output signals. The second improvement involves techniques to reduce the impact of gate leakage and charge injection currents in 90 and 65nm process technology nodes. At the 90nm node we demonstrate accuracy improvement of an order of magnitude for small test structures.

1 Introduction

The Charge Based capacitance measurement (CBCM) technique was first published in 1996 [1] and has since become a popular method for on-chip measurement of device and interconnect capacitance. Even with the introduction of copper interconnect and low dielectric material at 0.13 micron and 90nm technology nodes, delay from interconnect parasitic effects continue to dominate on-chip performance [2], [3]. To reduce the test structure area requirements, on-chip device switch matrix circuitry has been employed [4]; however this can induce excessive junction and gate leakage into the measurements. Also, a charge injection induced error-free CBCM technique [5] was developed, however this implementation may not be as area efficient as enabled by a bused or switch matrix approach. In this paper, we propose a solution which uses a bused architecture for reduced test structure area, and circuit design techniques to reduce the gate leakage and charge injection error associated with 90 and 65nm device technologies.