Analysis and methodology for multiple-fault diagnosis

In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

I. Introduction

THE PURPOSE of fault diagnosis is to determine the cause of failure in a manufactured faulty chip. A good diagnostic tool should effectively assist a designer in quickly and accurately locating the failure. The quality of a diagnosis impacts directly the time-to-market and the total product cost. Most of the studies on failure analysis have assumed a single defect. However, for present technologies and chip sizes, this assumption may not be true. Often, multiple defects on a failing chip better reflect the reality. It is also possible that certain single-location defects behave as multiple faults. Defects of this kind can be bridging defects that affect two fault locations, or via defects that may affect multiple branches, and which can be modeled as multiple faults at those branches.