Network-on-Chip: A New Paradigm for System-on-Chip Design

Network-on-chip is a novel category for on-chip communication where the abstraction of layered protocols is utilized to modularize the communication design. This also implies that the computation and communication are separated from each other. In this invited paper, the motivation for such an approach is explained, terminology within network-on-chip area is clarified, some of the proposed networks are analyzed, and the network-on-chip design aspects discussed.

I. Introduction

The increasing communication requirements on complex System-on-Chip (SoC) circuits have quickly forced designers from a paradigm shift to another. Systems based on asingle on-chip bus have made way to hierarchical multi-bus configurations and, finally, to on-chip networks. In addition to communication bandwidth and latency requirements, there are also demands for higher immunity to soft errors, timing variations and defects in nanometer scale integration. All these challenges await the emerging Network-on-Chip (NoC) paradigm.