Contents INTRODUCTION
In order to meet specifications, both feedback and feedforward methods were part of the initial design for the SNS Low-Level Radio Frequency (LLRF) control system [1]. Specifically, the LLRF hardware included five Programmable Logic Devices (PLDs) and dual Digital Signal Processors (DSPs) with direct access to the RF data sampled at 40 MHz [2]. The current SNS LLRF hardware is an extension of the system originally developed for the SNS front-end [3]: A single Xilinx Virtex II Field Programmable Gate Array (FPGA) implements a 40 MHz control loop with proportional and integral gain. It provides history buffers for the digital output as well as the measured forward, reflected, and cavity fields. Each buffer holds 512 pairs of in-phase and quadrature data samples, i.e. complex number waveforms. In normal operation, the resolution is configured to about per sample pair in order to capture the full RF pulse. A Motorola MVME2100 CPU board accesses the history buffers via VXlbus. Software based on the Experimental Physics and Industrial Control System (EPICS) toolkit[4] can present data to network clients via the ChannelAccess network protocol (CA) at up to 60 Hz, both the original data as well as computed amplitudes and phases. In practice, history buffer updates are usually reduced to 2 Hz and aligned with beam pulses.
