A precision CMOS amplifier using floating-gates for offset cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifier's architecture. The offset voltage of a single-stage folded cascode amplifier is reduced to plusmn25 muW in a 0.5mum digital CMOS process. The offset voltage drift is 0.5 muV over a period of 10 years at 25degC and varies by a maximum of 130muV over a temperature range of 170degC

I. Offset Removal

A floating-gate based offset cancellation scheme is presented that results in a continuous-time amplifier with longterm offset cancellation. A prototype amplifier has been fabricated with its offset voltage reduced to . The use of floating-gates for correcting mismatches in analog circuitry is particularly advantageous as it offers programmability, longterm retention and can be fabricated in a standard digital CMOS process. This approach involves no sampling and hence avoids such issues as charge injection, clock feedthrough and undersampling wideband noise that are serious limitations to autozeroing and correlated double sampling [4]. Also, unlike chopper stabilization [4], the proposed scheme is not limited to low-bandwidth applications while offering continuous-time operation with comparable offset reduction.