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A 90-nm variable frequency clock system for a power-managed itanium architecture processor | IEEE Journals & Magazine | IEEE Xplore

A 90-nm variable frequency clock system for a power-managed itanium architecture processor


Abstract:

An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a p...Show More

Abstract:

An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 41, Issue: 1, January 2006)
Page(s): 218 - 228
Date of Publication: 27 December 2005

ISSN Information:


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