Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding

This paper proposes a new scalable and efficient VLSI architecture for sub-pixel motion estimation. Based on this architecture, a modular and fully configurable motion estimation co-processor is also presented. The efficiency of such processing structure was assessed by embedding this circuit in a half-pixel accurate hierarchical motion estimation system using a two-step search procedure. Experimental results using FPGA devices show that the proposed motion estimation co-processor allows the estimation of motion vectors with half-pixel accuracy in real-time for the 4CIF image format

I. Introduction

A new efficient and scalable VLSI architecture for real-time sub-pixel motion estimation (ME) is proposed. This architecture requires only three sets of data for its operation: the initial coarser motion vector (MV) coordinates, the search area pixels surrounding that point and the current macroblock pixels. The coordinates of the starting point of the sub-pixel ME procedure can be computed in any other hardware or software application. Consequently, this novel architecture can be used to improve the accuracy of the ME process or to estimate local motion based on MVs predicted previous frames, in both hardware and hybrid software-hardware video coding systems.