Low-power adaptive bias/clock generator using 0.18/spl mu/m CMOS technology for multi-core continuous voltage and frequency scaling | IEEE Conference Publication | IEEE Xplore

Low-power adaptive bias/clock generator using 0.18/spl mu/m CMOS technology for multi-core continuous voltage and frequency scaling


First Page of the Article

Date of Conference: 28-28 July 2005
Date Added to IEEE Xplore: 12 December 2005
Print ISBN:0-7803-9345-7
Conference Location: Lausanne, Switzerland

First Page of the Article


I. Introduction

Continued technology scaling over the last three decades has helped to dramatically increase both the embedded functionality per chip area and the operating (clock) frequency. The functionality increase, combined with the diversification of system components and the advances of VLSI design techniques have eventually led to System-on-Chip (SoC) and Network-on-Chip (NoC) concepts with increasing complexity. Application demands and the continuous trend towards mobile, distributed systems have also made battery-powered portable electronic systems very popular and virtually ubiquitous. Nowadays such systems are widely used in many applications, such as mobile computing, information appliances as well as various industrial, medical and military applications. Unfortunately, the battery capacity has improved very slowly (a factor of 2 to 4 over last 30 years), while the systems became more complex and could incorporate more and more functionality over the same time frame. Thus, reducing energy consumption and extending battery lifespan have become a critical aspect of designing battery-powered systems. In addition, the cost of providing power (and associated cooling) has resulted in significant interest in power reduction even in non-portable applications which have access to a permanent power source [9]. Thus, power dissipation and power/performance trade-offs have emerged as major factors in determining the weight, the size and the life-time (autonomy) of portable devices. Managing power dissipation at the system level with dedicated power management units and/or algorithms can decrease energy requirements considerably and thus maximize battery life-time for portable components. Therefore, the power/energy management problem in large scale systems must be attacked both at the system level by means of global power management and optimization techniques, and at the transistor/circuit level by means of innovative structures to limit power dissipation [3], [7], [10].

References

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