I. Introduction
Charge carrier mobility continues to be a key parameter for MOSFET performance beyond the 90-nm technology node of the International Technology Roadmap for Semiconductors (ITRS). Typical electron mobilities in Si MOSFETs with gate dielectric are around 500–600 for inversion charge densities [1]. Mobility enhancement factors between 1.6 and 2 were measured using layers of strained SiGe or Ge, respectively [2] [3] [4]. However, the use of high- dielectrics such as reduces mobility; typical peak electron mobilities for Si bulk MOSFETs with gate dielectric are 200 [1], [5]. A future alternative to Si bulk and Si-based strained layer MOSFETs are layer structures based on III-V compound semiconductors [6], [7]. For the first time, the latest edition of the ITRS roadmap includes serious references to compound semiconductor based transistors as a “nonclassical” CMOS solution to continue long term scaling according to Moore's Law. Further, a number of RF applications, in particular in the wireless and mobile product space, will benefit from performance enhancements potentially provided by III-V MOSFETs. NMOSFET layer structure. The -dopings are indicated by dashed lines. This letter reports on electron mobilities as high as 6,155 in GaAs enhancement mode NMOSFET structures employing a high- dielectric () and a strained InGaAs channel layer with a thickness of 10 nm.