Some alternative techniques for hardware address generators for digital signal processors

Existing fast methods for generating the address sequences required for DSP (digital signal processing) applications are limited by use of both address arithmetic techniques employing ALUs (arithmetic logic units) and loop techniques. The alternative table-lookup method is limited due to table size, due either to the data block size or to the number of algorithms required. The alternatives presented by the author have the advantage of using counters which are potentially much faster than the adders utilized in ALU design. This is achieved without loss of generality other than restriction to a block size that is a power of two. In addition, avoidance of loops allows a fast pipeline approach to be used to further maximize speed. Parallel, parallel/serial, and serial approaches to this technique provide the designer with a number of cost/speed alternatives.<>