Novel device isolation technology with selective epitaxial growth

A fine device isolation technology for small geometry VLSIs using selective epitaxial growth (SEG) is described. The epitaxial silicon layer is selectively grown on a bulk silicon surface surrounded with a SiO2isolation wall under reduced pressure using SiH2Cl2-H2-HCl systems. Polysilicon gate MOSFETs are successively fabricated on the epitaxial silicon layer. The p-n junction characteristics are reasonable, according to theoretical values, and the leakage current along the lateral SiO2wall is negligibly small. The subthreshold characteristics for parasitic devices with submicron geometry gives the same slope value as that for conventional devices.