Novel instructions and their hardware architecture for video signal processing

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced by about 20/spl sim/25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute the 1D forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.

I. Introduction

With the rapid progress of semiconductor technology, the market of Application-Specific Signal Processor (ASSP) is dramatically growing. Once algorithms have been fixed, custom Application-Specific Integrated Circuit (ASIC) chips have been implemented to reduce the cost, size, and power consumption of systems. However, custom ASIC solutions have been found inadequate to upgrade standards since they should be redesigned. With the rapid increase in clock speed it has become feasible to keep the functionality entirely in a programmable DSP, greatly improving time-to-market and allowing faster changes and upgrades. ASSP can compromise advantages of custom ASIC chips and general DSP chips [1] [2] [3]. In other words, ASSP chips adopt high performance and low power of ASIC chips and flexibility of DSP chips.