Contents I. Introduction
Mixed-Signal integrated circuits have been demonstrated to provide high-performance system solutions for various applications such as wireless communications and high-speed communication backbones. The continued scaling and improvement of semiconductor processes have made it possible to integrate RF, analog, and digital circuitry on a common silicon substrate and create system-on-chip (SoC) solution for various mixed-signal applications. Furthermore, RF and high-speed integrated circuits in silicon-based CMOS technology are increasingly desirable due to the fabrication cost advantage. However, unlike RF circuits on low-loss substrates, such as alumina and GaAs, the lossy nature of the semiconducting silicon substrate may have a significant impact on the loss and dispersion characteristics of on-chip interconnects in RF, high-speed analog-signal, and mixed-signal integrated circuits. From the simulation results for interconnects near substrate [1], it can be seen that the influence of frequency-dependent parameters to high-speed circuits becomes more and more serious because the signals in high-speed digital circuits have so short rise and fall times that the signals possess a broad frequency spectrum. Hence, accurately extracting frequency-dependent parameters for the interconnects based on lossy substrate becomes a key step for on-chip design. With regard to the interconnects embedded in general CMOS process, the physical equivalent circuit shown in the Fig. 1(a) is composed of two parallel parts of circuits. One part is the capacitances , in the layer and in the protective layer. The other part is the capacitance representing the layer, in series with the capacitance and parallel conductance to represent the semiconducting silicon substrate. Even though each individual fixed capacitance and conductance within Fig. 1(b) is frequency independent, the merging admittance in the simple equivalent extracted circuit model in Fig. 1(c) becomes a complex function of frequency. Thus, the extracted susceptance and conductance are highly frequency dependent and is called capacitance; here, parallel with conductance because the imaginary part of admittance is positive and it acts like a capacitor. In this paper, we provide a novel, simple, and accurate closed-form Green's function to extract the parameters for arbitrary dimensional interconnects and transmission lines embedded in the general CMOS process. The hierarchical algorithm is further developed to accelerate the computational convergence of our proposed double-image Green's function based on the fact that the electric field decreases as the distance increases and the potential due to a cluster of particles is the sum of the potential due to each individual particle. Extracted frequency-dependent capacitance and conductance in typical standard CMOS technology. Schematic presentation of typical 0.25- CMOS process. Schematic presentation of typical 0.18- CMOS process.
