I. Introduction
Electrostatic DISCHARGE (ESD) phenomenon is originated from the transfer of electrostatic charges between two objects with different electrical potentials, which results in damage to integrated circuits (ICs) due to large energy dissipation in an extremely short time of less than 150 ns. ESD failure will become more serious reliability concern in nanoscale CMOS IC products. Common ESD failures are catastrophic, leading to immediate malfunction of IC chips caused by either thermal breakdown in silicon and/or melting metal interconnects due to high-current transient, or dielectric breakdown in gate oxide due to high-voltage overstress [1]. The ESD specifications of commercial IC products are generally higher than 2 kV in human-body-model (HBM) [2] ESD stress and 200 V in machine-model (MM) [3] ESD stress. Therefore, in order to provide the effective ESD protection for CMOS ICs against unexpected ESD damages in the internal circuits of CMOS ICs [4]–[10], the on-chip ESD protection circuits have to be designed and placed around the input, output, and power pads to clamp the overstress voltage across the internal circuits, and to provide a low impendence path to ground for discharging the ESD current of several amperes. The locations of the ESD protection circuits to achieve whole-chip ESD protection for CMOS ICs are illustrated in Fig. 1 [11].