Logic testing of CMOS structures

The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic circuits are taken into consideration. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program