Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

I. Introduction

With THE scaling of CMOS into sub-90-nm technology nodes, control over short-channel effects (SCEs) becomes increasingly difficult in planar-bulk architecture. In order to achieve the target subthreshold performance [1], high channel doping concentrations are needed in planar bulk technologies. This gives rise to significant dopant-induced fluctuations in threshold voltage, and degradation in channel mobility [2]. A transition from planar bulk to the double-gate architecture could facilitate the target subthreshold performance while also keeping the channel-doping concentration low, if ultrathin Si films and metal gates can be used to control SCEs and adjust the threshold voltage [3], respectively.