Abstract:
Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induc...Show MoreMetadata
Abstract:
Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift.<>
Published in: IEEE Transactions on Electron Devices ( Volume: 39, Issue: 7, July 1992)
DOI: 10.1109/16.141235
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