Abstract:
IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promo...Show MoreMetadata
Abstract:
IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.
Date of Publication: 15 November 2004
Electronic ISBN:978-1-5044-0930-8
Persistent Link: https://xplorestaging.ieee.org/servlet/opac?punumber=9651
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