1. Introduction
Transition faults are defined to be caused by defects that cause a logic value transition (0→1 transition or 1→0 transition) on a net to be delayed such that the transition does not reach a primary output (PO) or scan flip-flop. If the defect causes the 0→1 (1→0) transition to be delayed, then the fault is called slow-to-rise (slow-to-fall) or STR (STF) transition fault. Generally speaking, a transition fault requires a pair of test patterns { } to be tested. is required to set the fault-site to the initial value, and is needed to launch the appropriate transition on the fault site and also to detect the fault-effect at a PO. For full-scan designs, is a single vector, while for partial scan and non-scan designs, may be a sequence of test vectors. Scan-based transition tests can be applied in three different schemes: Broadside[1], Skewed-Load[2], and Enhanced-Scan[3]. In. the context of stuck-at faults, to detect a STR (STF) transition fault, test sequence must excite a stuck-at-l (stuck-at-0) on the fault site, and must detect a stuck-at-0 (stuck-at-1) on the fault-site. Independent of the testing scheme that is employed to detect transition faults, if the initial sequence or the final test sequence cannot be generated for a particular transition fault, the fault would be untestable.