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Identifying untestable transition faults in latch based designs with multiple clocks | IEEE Conference Publication | IEEE Xplore

Identifying untestable transition faults in latch based designs with multiple clocks


Abstract:

This work presents a novel technique to identify functionally untestable transition faults in latch based designs with multiple clock domains, bringing to light unaddress...Show More

Abstract:

This work presents a novel technique to identify functionally untestable transition faults in latch based designs with multiple clock domains, bringing to light unaddressed issues related to untestable fault identification in such design environments. We also introduce and provide a solution to a new variant of un-testability analysis wherein "architectural constraints'' are absorbed during the analysis. We give our tool the capability of handling transition faults resulting from defects of varying sizes, and evaluate our tool for various industrial circuits. The proposed algorithm is compared with a state-of-the-art sequential ATPG tool, and our method has shown much better performance both in the context of scan ATPG and functional test development. Results indicate that the proposed technique identifies considerably more untestable transition faults than those that can be deduced from the knowledge of untestable stuck-at faults. Additional insights from our results point to a greater need to eliminate untestable transition faults as compared to stuck-at faults, for more efficient test pattern generation and accurate coverage computation.
Date of Conference: 26-28 October 2004
Date Added to IEEE Xplore: 31 January 2005
Print ISBN:0-7803-8580-2
Conference Location: Charlotte, NC, USA

1. Introduction

Transition faults are defined to be caused by defects that cause a logic value transition (0→1 transition or 1→0 transition) on a net to be delayed such that the transition does not reach a primary output (PO) or scan flip-flop. If the defect causes the 0→1 (1→0) transition to be delayed, then the fault is called slow-to-rise (slow-to-fall) or STR (STF) transition fault. Generally speaking, a transition fault requires a pair of test patterns { } to be tested. is required to set the fault-site to the initial value, and is needed to launch the appropriate transition on the fault site and also to detect the fault-effect at a PO. For full-scan designs, is a single vector, while for partial scan and non-scan designs, may be a sequence of test vectors. Scan-based transition tests can be applied in three different schemes: Broadside[1], Skewed-Load[2], and Enhanced-Scan[3]. In. the context of stuck-at faults, to detect a STR (STF) transition fault, test sequence must excite a stuck-at-l (stuck-at-0) on the fault site, and must detect a stuck-at-0 (stuck-at-1) on the fault-site. Independent of the testing scheme that is employed to detect transition faults, if the initial sequence or the final test sequence cannot be generated for a particular transition fault, the fault would be untestable.

References

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