Contents I. Introduction
Over THE past three decades, silicon MOS-based integrated circuits, such as microprocessors, have consistently delivered greater functionality at higher performance and lower cost per function. An empirical observation called Moore's Law [1] is commonly quoted to highlight the exponential rates of increase in circuit speed and integration density as MOS transistors have scaled down in channel length. However, sometime within the next five years, traditional CMOS technology is expected to reach limits of scaling. As channel lengths shrink below 50 nm [2], complex channel profiles are required to achieve desired threshold voltages and to alleviate the short-channel effects [3]. Some nonclassical transistor structures will likely take over due to their delivery of higher performance with lower leakage than traditional scaled CMOS approaches. For this purpose, companies including Intel, IBM and Hitachi have explored the performance and scalability of novel MOSFET structures for sub-50-nm devices. New transistors—particularly double-gate and ultrathin-body (UTB) MOSFETs offer paths to further scaling, perhaps to the end of the 2003 International Technology Roadmap for Semiconductors (ITRS) [4]. Double-gate transistors allow twice the drive current with an inherent coupling between the gates and the channel that makes the design more scalable. In UTB-silicon-on-insulator (SOI), power consumption is drastically reduced along with leakage current. However, there are still a number of issues that need to be resolved in, for example, the fabrication and the design of fully depleted (FD)-SOI device structures.
Threshold voltage in bulk-MOSFETs with polysilicon gates is traditionally controlled through channel profile engineering [5]. However, in a sub-100-nm FD-SOI device, this leads to problems such as channel dopant fluctuation, subthreshold swing degradation, mobility reduction and threshold voltage sensitivity to oxide thickness. We have already shown that even in conventional transistors there is a significant mismatch in the threshold voltage between devices with different number and different distribution of the impurity atoms [6]. It is, thus, necessary to examine the role of unintentional doping on the narrow-width FD-SOI device operation.
As devices scale, quantum effects are known to have significant impact on device characteristics. Gate tunneling, band-to-band tunneling and quantum confinement of carriers (in a potential well close to the surface) in bulk-MOS are well understood and modeled in most commercial and academic device simulators [7]–[9]. In the case of double-gate devices, carriers are always confined in a very small layer of semiconductor, and hence quantum effects assume greater importance. Furthermore, classical transport models, such as drift-diffusion, become invalid at such small dimensions and quantum transport models become necessary.
