Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.

I. Introduction

Embedded nonvolatile memory (NVM) is finding increasing use in a wide array of integrated circuits with applications ranging from a few bits in analog trim applications, to megabits for data or code storage [1]. Although there are many technology choices for embedding NVM, virtually all presently available technologies need process modifications and additional mask steps, such as thicker oxides and additional implants, from the baseline logic or mixed-signal CMOS processes. The result is more costly processing and lower chip yields, and is not economical in many designs where only a small amount of NVM is needed. It is thus very desirable to develop NVM in standard CMOS logic or mixed-signal processes. There have been previous attempts in this regard, including a one-time-programmable (OTP) memory produced in standard 0.25- process, [2] but few many-time-programmable (MTP) NVM in logic process have been reported [3].