Design of a lattice decoder for MIMO systems in FPGA

Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using an FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7 Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.

1. Introduction

Muliple-input multiple output (MIMO) wireless systems use multiple antennas in both transmitters and receivers. Recently, the interests in MIMO systems have exploded because of the huge capacity of this multienvironment system. Lattice theory and coding theory are applied to encode and decode in the multiple-antenna digital transmission systems. Layered space time receiver structures and coding schemes have allowed the MIMO systems to approach the theoretical capacities.