Contents I. Introduction
Recently, dual-bit charge-trapping memory cells with oxide–nitride–oxide (ONO) dielectrics have been proposed and realized for very high-density data storage applications [1], [2]. In these devices, charge is injected and stored locally in the nitride trapping layer close to the two pn junctions yielding two bits per cell. As a result, the requirements on lithography compared to the mainstream single level NAND floating-gate memory arrays [3], [4] for the same storage density are relaxed, thus allowing for a very competitive cost ratio. However, the strong electric fields between source and drain during programming and erasing as well as lateral charge leakage are challenging scalability issues. In contrast, devices with double or tri-gate architectures [see Fig. 1(a)] improve the electrostatic gate control of the channel region [5]– [7] and are able to screen efficiently the electrical fields between source and drain. Further, the vertical structure permits high readout currents even at very small bitline pitches. In addition, the electrostatic interaction between the stored charges of neighboring memory cells is efficiently shielded by the surrounding gate which effectively acts as a “ground plane” between the cells.
(a) Schematic tri-gate memory device with ONO dielectric. The ONO thickness of the fabricated devices is 3/4/4.8 nm, while nm and nm. (b) Top view of tri-gate memory device operated in dual-bit mode.
