Power estimation and thermal budgeting methodology for FPGAs

The method used for power estimation and thermal budgeting on an FPGA product line, fabricated using 90 nm technology, is described in this paper. It addresses the reasons why state-of-the-art processes create power concerns on FPGAs, and describes methodologies that provide more relevant power and junction temperature estimations. Finally it suggests what can be done to improve the power budget and to balance the trade-offs between power and performance.

Introduction

With the continual evolution of process technologies from 90nm and beyond, there has been sufficient evidence of increasing process complexities (1). In addition to this, 90nm fabrication costs are rising. The total cost of a set of 40 masks can approach 1.5 million dollars, making ASICs financially justifiable only for very high volume and high revenue designs. This favors FPGA adoption in previously low-medium volume ASIC-centric sockets. However, the increased process complexities/deviations at the 90nm node and beyond have created design challenges for FPGAs. As the transistor dimensions shrink, leakage currents have increased exponentially. Sub-threshold leakage, which was largely considered negligible in older technologies, has become a major concern at the 90nm process, especially on high gate-count devices like FPGAs. Higher current leads to higher junction temperature, which causes performance degradation, reliability issues such as electro-migration or even instant damages to the silicon and package. It has therefore become essential to have a 90nm-centric power analysis strategy for FPGAs, similar to the efforts targeting other semiconductor devices (2) (3).