Characterization of soft errors caused by single event upsets in CMOS processes

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

1 Introduction

Electronic circuits encode information in the form of a charge stored on a circuit node or as a current flowing between two circuit nodes. For example, one bit of static memory contains two nodes that store two complementary charges corresponding to logic “1” and logic “0.” The bit values “1” and “0” can be stored as node charges “10” and “01,” respectively. A static memory makes use of feedback to continuously replenish the charge on both nodes. The stored bit value can be preserved indefinitely as long as noise originating from the interconnect coupling or other sources does not overwhelm the stored charge. During the write operation, the state is intentionally modified by coupling the charge via bitlines.