5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

I. Introduction

Continual transistor scaling has led to the demonstration of sub-10nm CMOS devices using transistor structures such as thin-body SOI transistor, double gate FinFET, and even conventional transistors on bulk substrates [1] [4]. In transistors with nano-scale physical gate length , it is important that the channel conductance is predominantly controlled by the gate electrode, and not by the drain. For SOI devices, this is achieved by reducing the silicon body thickness. This approach, however, trades off low parasitic resistance for better control of short channel effects. Double gate transistor [1], tri-gate transistor [5] or omega FinFET [6] are alternative device structures to improve the short channel control. In this work, a nanowire FinFET is proposed for sub-10 nm scaling. Fig. 1 illustrates the evolution of device structures from double-gate to omega-shaped to nanowire FinFETs, where the criterion of fin thickness is successively relaxed from to and to .