Contents I. Introduction
AS THE DEMANDS for low-power high-density high-speed dynamic random access memory (DRAMs) increase for the mobile and high performance applications, low voltage operation is mandatory as predicted in the International Technology Roadmap for Semiconductors (ITRS) 2002. Dual-gate CMOS is also essential for the low-voltage operation because low threshold voltage p-channel MOSFET can not be made by buried channel but by surface channel. Dual-gate CMOS processes are widely applied to logic, SRAM large-scale integrations (LSIs) [1]–[10] and embedded DRAMs which have relatively small restrictions on density and cost compared to commodity DRAMs [11]–[14]. Key process technologies of conventional dual-gate CMOS are thermal budget suppression to control impurity diffusion, simultaneous doping of gate and source/drain with undoped poly-Si, and the salicide process. This conventional process is not suitable for the commodity DRAM fabrication because it requires large amount of thermal treatment to suppress junction leakage and satisfy the data retention time requirement. Large thermal budget induces B penetration from the -doped gate to the channel through the thin gate oxide. Reduction of thermal process causes fatal problem to the mobile and graphic DRAMs because they require even longer retention time and lower power consumption. A capping SiN layer is necessary on a poly- stacked gate to reduce DRAM cell size using self-aligned contact (SAC) scheme. However, it prevents the gate from doping simultaneously during the source/drain implantation. Therefore, for dual-gate DRAM fabrication, two additional lithography steps for gate doping are necessary using conventional CMOS processes resulting in the process cost increase [13], [14]. In addition, it is well known that B penetration through the thin gate oxide is enhanced due to the fluorine in WSi layer.
