CMOS circuit performance enhancement by surface orientation optimization

With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-/spl kappa/ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-/spl kappa/ interface. Additional concerns including layout area and device reliability are discussed.

I. Introduction

CMOS CIRCUITS have traditionally been fabricated on silicon substrates with a (100) crystalline orientation due to their high electron mobility and reduced interface trap density. Hole mobility, however, is very low in the (100) orientation, but can be improved by using alternative surface orientations [1]–[3]. The potential use of alternative surface orientations has been studied in the past [2], [4], [5] and shown to be beneficial in improving pMOSFET device performance. However, practical application of such a scheme has been limited by the degradation of device reliability due to interface traps [6]. Furthermore, in order to achieve different orientations, it could be necessary to fabricate devices on trench sidewalls [4], [5]. Recently, it was reported that with gate dielectrics thicknesses now in the direct-tunneling regime, reliability is no longer dependent on the silicon crystal orientation [7]. This removes the primary limitation of non-(100) silicon substrates, thus making them a viable option for the optimization of CMOS circuits.