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The influence of heavily doped buried layer implants on electrostatic discharge (ESD), latchup, and a silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe technology | IEEE Conference Publication | IEEE Xplore

The influence of heavily doped buried layer implants on electrostatic discharge (ESD), latchup, and a silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe technology


Abstract:

This paper will demonstrate the effect of heavily doped buried layers (HDBL) on electrostatic discharge protection, latchup, and silicon germanium (SiGe) heterojunction b...Show More

Abstract:

This paper will demonstrate the effect of heavily doped buried layers (HDBL) on electrostatic discharge protection, latchup, and silicon germanium (SiGe) heterojunction bipolar transistors (HBT). Heavily doped buried layers (HDBL) implants, in prior publications, have demonstrated improvements in latchup robustness in low-doped substrate wafer technology. The influence of HDBL on MOSFET ESD protection has also been demonstrated. In this paper, the focus is the influence of HDBL implants on BiCMOS SiGe HBT devices and derivatives from a functionality, ESD and latchup perspective in a BiCMOS SiGe technology as well as relevance to RF and MS CMOS technology. Experimental results will be shown for different heavily doped buried layer implant doses and energies.
Date of Conference: 25-29 April 2004
Date Added to IEEE Xplore: 26 July 2004
Print ISBN:0-7803-8315-X
Conference Location: Phoenix, AZ, USA

Introduction

BiCMOS SiGe HBT technology and RF CMOS technology must be placed in p-substrate to provide noise isolation between digital, analog and RF circuits. Low doped substrate wafers are needed to prevent the digital circuits to induce noise in the analog and RF circuitry. BiCMOS and mixed signal (MS) CMOS technologies have been on low doped wafers to provide noise isolation and high quality factor passives. The “Q” of inductor elements and other RF passives are important. At the same time, semiconductor process solution must maintain good reliability to prevent CMOS latchup [1]–[18]. With semiconductor device scaling of p+/n+ spacing, shallow trench isolation (STI) depth, and lower substrate doping concentration, lower latchup margin in advanced technologies exists today compared to prior technology generations [18]–[21].

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References

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