An adaptive path delay fault diagnosis methodology [logic IC testing]

A framework to adaptively perform delay fault diagnosis is introduced. We propose a methodology to perform diagnosis taking into account the effect of test vectors on the propagation delay along a path. An ATPG capable of generating test vectors that cannot be invalidated due to process variations in the submicron technology is used for diagnosis purposes. The proposed framework also has the ability to generate tests that can take care of delay faults induced by noise. Experimental results on the ISCAS'85 benchmarks shows the effectiveness of the proposed technique.

1 Introduction

With the advent of deep-submicron technology, testing the performance of an integrated circuit (IC) has become a difficult task. Even small process variations can cause a fault in the circuit. Therefore before mass production of the IC, a small number (first silicon) is produced to perform the various tests and check for the performance of the IC. The check is performed by applying test vectors and comparing the expected output to the sampled output. In this paper, without loss of generality, a slow-fast test application methodology on the combinational component of the digital synchronous circuit is assumed. The concepts presented in this paper can be extended with trivial modifications to handle at-speed test application methodology. Assuming that the chip is functionally correct, i.e., the chip produces the correct output if given enough time, any fault observed at the output is the result of one or more delay faults in the circuit under diagnosis(CUD). The process of locating input-output paths in the chip that caused the delay fault is termed as delay fault diagnosis. In this paper we use the path delay fault model (PDF) for delay fault diagnosis.