Scaling analysis of phase-change memory technology

The scaling capability of chalcogenide-based phase-change memory (PCM) is discussed. Experimental and numerical results are presented, showing that the reset current scales down with the device contact area, reaching values as low as 50 /spl mu/A. The impact of thermal cross-talk between adjacent bits is investigated, showing that thermal disturbs will not limit the scaling of PCM down to the 65 nm technology node. Finally, scaling rules for the PCM technology are provided.

Introduction

Phase-Change Memory, also called Ovonic Unified Memory (OUM), is a novel non-volatile semiconductor technology based on reversible phase transitions of a thin-film chalcogenide material (Ge₃Sb₂Te5-GST)((10) –(3). Fig. 1 shows the schematic cross-section of an OUM cell array for high density memories. The cell is essentially a resistor with a low-field resistance that changes by orders of magnitudes depending on whether the GST in the active region is crystalline or amorphous. In memory operation, cell read out is performed at low bias. Programming requires instead a relatively large current, in order to heat-up the GST, leading to a local phase change. The reset current, that is the current required to switch from the crystalline to the amorphous state, is a concern together with the potential impact on data retention of thermal disturbs between adjacent bits. In this paper the scaling capabilities of the OUM technology are investigated for the first time. We show that no significant thermal crosstalk is expected for devices at the 65 nm technoogy node, while the reset current can be safely scaled down almost linearly by reducing the device contact area. Figure 1:

Schematic cross section of the device structure. Note the thermal cross-talk between the adjacent bits.

Figure 2:

Temperature distribution simulated near the GST/heater interface.