Contents Introduction
Gate-length scaling has rapidly accelerated toward the sub-100m regime. Several demonstrations of devices with gate-lengths well below 20nni have already been reported using a variety of different architectures [1]–[4]. The UTSOI device is an attractive option because it ensures SCE control through scaling which also provides the additional benefits of lower junction capacitance and steeper sub-threshold swing. However, several issues must be addressed in order to achieve high performance UTSOI devices. These issues include high external resistance, low channel carrier mobility, inappropriate threshold voltages and leaky gate oxides. In the work presented here, the external resistance issue is addressed by forming an offset spacer and growing selective epitaxial silicon to minimize the region of UTSOI outside the channel. We call this integration scheme Raised EXtension (REX). REX is used to demonstrate improved performance for UTSOI MOSFETs with gate-lengths down to 8nm. Carrier mobility is examined as a function of and also temperature. Results obtained at realistic operating temperatures demonstrate that the practical range of silicon channel thickness may be extended further than previously predicted. This will likely enable additional gate-length scaling for future UTSOI technologies. A replacement gate scheme incorporating a tungsten damascene process and HfO2 gate dielectric is used to demonstrate UTSOI devices with appropriate threshold voltages and gate dielectrics with nm for the first time.
