Abstract:
A low cost patent pending 5-bit digital phase shifter has been developed for application in DBS receiving phased array antennas. New simplified loaded line architecture o...Show MoreMetadata
Abstract:
A low cost patent pending 5-bit digital phase shifter has been developed for application in DBS receiving phased array antennas. New simplified loaded line architecture of less significant bit is proposed. The new circuit mitigates PCB technology limitations and reduces the number of switching components, which are low cost discrete p-HEMT FETs. TRL measurement technique was employed for extraction of the cold FET two states parameters. The digital 5-bit phase shifter operates in full satellite TV band from 10.7 to 12.75 GHz and has following main parameters: insertion loss 6dB, insertion loss deviation /spl plusmn/1.4dB, average RMS phase error 3/spl deg/ and worst-case input/output return loss 11dB. The control of the device is CMOS(5V) compatible with setting time less than 70ns.
Date of Conference: 07-07 October 2003
Date Added to IEEE Xplore: 06 February 2004
Print ISBN:1-58053-834-7