Non-enumerative path delay fault diagnosis [logic testing]

The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with a validated non-robust test may together with fault free robustly tested faults be used to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero suppressed binary decision diagram. The proposed method is space and time non-enumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS'85 benchmarks show that the proposed technique is on an average least three times more efficient in improving the diagnostic resolution than existing techniques.

1 Introduction

With the advent of deep-submicron technology, testing for the performance of an integrated circuit (IC) has become a difficult task. Even small process variations can cause a fault in the circuit. Therefore before mass production of the IC, a small number (first silicon) is produced to perform the various tests and check for the performance of the IC. The check is performed by applying test vectors and comparing the expected output to the sampled output. We assume a slow-fast test application methodology on the combinational component of the digital synchronous circuit and that the circuit under diagnosis is functionally correct. The process of locating the region in the chip that caused the delay fault is termed as delay fault diagnosis.