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Bringing communication networks on a chip: test and verification implications | IEEE Journals & Magazine | IEEE Xplore

Bringing communication networks on a chip: test and verification implications


Abstract:

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NO...Show More

Abstract:

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips' AE THEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and testing and verifying the other components of the SOC. This article is concluded with our experiences with NOCs and a description of ongoing work within Philips in this emerging field.
Published in: IEEE Communications Magazine ( Volume: 41, Issue: 9, September 2003)
Page(s): 74 - 81
Date of Publication: 15 September 2003

ISSN Information:


Introduction

High-performance networking requires dedicated hardware with tremendous computational and communication performance. Network components such as network interfaces and routers are complex systems that are built in a modular fashion by combining many application-specific integrated circuits (ASICs). With increasing packet throughput, ASIC performance must increase. Moreover, trends toward differentiated services and higher quality of service require additional performance. Examples are more discerning packet classification, traffic shaping, network management, and debug. To address these issues networking ASICs must become more versatile and programmable, often evolving toward network processors.

References

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