High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

I. Introduction

The SIA's ITRS 2001 predicts that sub-50 nm CMOS devices (90, 65 nm node CMOS) will have the current drive of 900 in nFET and 400 in pFET at , respectively. There are already some reports on sub-50 nm CMOS devices [1]–[4]; however, they did not show sufficiently clear guidelines to achieve such high performance with supplied voltage lowered below 1.0 V.