Abstract:
The design of an integrated smart sensor called PASIC is described. The basic idea is to integrate a 2-D image-sensor array with a linear A/D (analog-to-digital) converte...Show MoreMetadata
Abstract:
The design of an integrated smart sensor called PASIC is described. The basic idea is to integrate a 2-D image-sensor array with a linear A/D (analog-to-digital) converter array and a linear processor array in a single chip. The current version of PASIC contains 128 parallel processors with a 128*128-b memory, 128 8-b A/D converters, and a 128*128 photo sensor array. Two 128*8 bidirectional shift registers are used for communication between processor elements and I/O (input/output). A memory-bus organized architecture is used, having been proven as an efficient VLSI architecture for a SIMD (single instruction, multiple data) bit-serial processor array.<>
Date of Conference: 01-03 May 1990
Date Added to IEEE Xplore: 06 August 2002
