Field-Effect Passivation of GaN-Based Blue Micro-Light-Emitting Diodes

We demonstrate field-effect passivation (FEP) of GaN-based blue $\mu $ LEDs by incorporating an additional metal-oxide-semiconductor gate structure on the sidewalls. This approach allows for active control of surface band bending at the sidewalls, thereby modulating carrier trapping and de-trapping. We observe that applying a negative gate voltage $(V_{G})$ facilitates electron de-trapping, leading to a reduction in surface recombination and a corresponding decrease in current, as evidenced by an enhanced external quantum efficiency (EQE). Conversely, applying a positive $V_{G}$ results in the opposite effect.

SECTION I. Introduction

GaN-based micro-light-emitting diodes ($\mu $ LEDs) are garnering significant attention as candidates for next-generation display technology, particularly in virtual reality (VR) and augmented reality (AR) devices, due to their superior properties [1], [2], [3], [4]. However, size-dependent efficiency degradation, characterized by a decrease of external quantum efficiency (EQE) and an increase of current density corresponding to the maximum EQE $(J_{max.\, EQE})$ has been observed as pixel sizes are reduced [5], [6]. This degradation arises from increased surface-to-volume ratios and the effects of the surface conditions. The pixelization process of $\mu $ LEDs, involving inductively coupled plasma reactive ion etching (ICP-RIE), introduces crystallographic defects that enhance non-radiative recombination centers [7], [8], [9]. Even with surface passivation schemes, surface-state-induced band bending persists, complicating efforts to fully address this issue. Given the infeasibility of achieving perfect crystallographic curing in practical scenarios and the enduring presence of surface band bending, the understanding of the sidewall carrier dynamics, particularly for GaN-based $\mu $ LEDs, remains incomplete compared to the group IV semiconductors. To comprehend carrier dynamics, active control of surface band bending and its impact on device efficiency is required, achievable through a metal-oxide-semiconductor (MOS) structure on the sidewall of the mesa [12], [13].

In this study, we demonstrate field-effect passivation in GaN-based blue $\mu $ LEDs by incorporating a MOS gate structure on the sidewall. This allows for the active control of band bending at the sidewall by applying a gate bias. The experimental results indicated that applying negative gate bias $(V_{G})$ can facilitate electron de-trapping, leading to a significant reduction of surface recombination and the corresponding recombination current, evidenced by the increase of EQE at the low current density region and the reduction of $J_{max.EQE}$ in $10\times 10~\mu $ m² sized $\mu $ LEDs and this effect will be much considerable as the size further decreases. This study underscores the importance of eliminating electrons in the sidewall or the electron trap to mitigate the size-dependent efficiency degradation.

SECTION II. Experimental

The epitaxial structure of GaN-based blue $\mu $ LEDs was grown on an 8-inch Si (111) substrate. The epitaxy layers from the bottom are composed of AlN/AlGaN buffer layer, undoped GaN buffer layer, Si-doped n-type GaN layer, InGaN/GaN strain relaxation superlattices layer, InGaN/GaN multiple quantum well (MQW) layer, AlInGaN electron blocking layer (EBL) and Mg-doped p-type GaN layer.

To fabricate the field-effect passivated (FEP) $\mu $ LEDs, the epitaxy layers were cleaned and 100 nm thick ITO was deposited using e-beam evaporator and annealed for 5 min at 550°C in air ambient. $\rm SiO_{2}$ hard-masking layer was deposited and patterned using photolithography and etched using buffered oxide etch. Then, the sample was etched using ICP-RIE under BCl₃/Cl₂ plasma conditions at room temperature. The samples were passivated using KOH (2mol/L) for 1 hour at 70°C in a temperature-controlled water bath. Then, the $\rm SiO_{2}$ hard mask was removed using buffer oxide etched, and sequentially loaded to the atomic layer deposition (ALD) chamber to deposit 50 nm thick Al₂O₃. This oxide layer was patterned and etched. Then, post-deposition annealing was conducted at 300°C for 10 min in chamber condition of 1Torr N₂. Without the post-deposition annealing process, the interface trap between the semiconductor layer and gate oxide layer can deteriorate gate driving strength, leading to negligible gate effect with the $V_{G}$ applied. For gate metal pad, W and Al were deposited using DC sputtering and thermal evaporator, respectively, and were lifted off using acetone. Regarding the selection of gate oxide and metal, it was chosen for its commonness in Si and GaN transistors industry and researches. Yet, further optimization regarding the material selection and gate oxide thickness might be required to reduce $V_{G}$ . Then, 50 nm thick Al₂O₃ is deposited using ALD process, and via patterning and etching were conducted to expose the n-type GaN. Then, Ti/Au was deposited for the anode and cathode. The electrical measurements were conducted using Keysight B1500A, and the optical properties were measured using integrating sphere, an optical spectrum analyzer, and a calibrated Si-photodiode.

SECTION III. Results and Discussion

The device schematic and optical microscope image of the fabricated FEP $\mu $ LEDs with dimensions of $10\times 10~\mu $ m² is presented in Fig. 1(a-b), and the SEM images are shown in Fig. 1(c). Both images illustrate well-aligned oxide and metal layers. Fig. 1(d) and (e) show the cross-section SEM images along the line X1 and X2 marked in Fig. 1(c), respectively. The images show perfect gate metal step coverage along the mesa sidewall.

FIGURE 1.

(a) Schematic of FEP $\mu $ LEDs. (b) Optical microscope image of fabricated FEP $\mu $ LEDs with mesa size of $10\times 10~\mu $ m². (c-e) (c) top view and (d-e) cross-section view of the fabricated FEP $\mu $ LEDs.

The void observed between W and Al is attributed to the ion milling process of the focused ion beam.

Fig. 2(a-b) shows the current density-voltage characteristics of FEP $\mu $ LEDs with sizes of $100\times 100~\mu $ m² and $10\times 10~\mu $ m². Under forward bias with no gate bias applied, no significant leakage path is observed regarding electrical current, indicating the fabrication of high-quality devices. Furthermore, a current level of pA range was confirmed when sweeping the voltage between the anode/gate metal and cathode/gate metal, indicating the absence of a short path between the gate metal and anode/cathode. To modulate the band bending in the sidewall region, various $V_{G}$ was applied to the gate metal, and the current density under forward bias.

Under the forward bias condition, the $100\times 100~\mu $ m² sized FEP $\mu $ LEDs show negligible change in current density above the turn-on voltage due to the dominancy of bulk electrical current flow, but an increase in leakage current under the turn-on voltage near 1V could be observed. Conversely, significant change could be observed when $V_{G}$ was applied to $10\times 10~\mu $ m² sized FEP $\mu $ LEDs. With a gradual increase in positive $V_{G}$ in steps of 1V, the current density increased from 0.583 A/cm${^{{2}}}~(V_{G}{=}0$ V) to 0.965 A/cm${^{{2}}}~(V_{G}{=}4$ V) at a forward bias of 2.5V. In contrast, with a gradual decrease in negative $V_{G}$ in steps of −1V, the current density decreased from 0.583 A/cm${^{{2}}}~(V_{G}{=}0$ V) to 0.199 A/cm${^{{2}}}~(V_{G}{=} -4$ V). No variation in current density under the turn-on voltage near 1V could be observed as in $100\times 100~\mu $ m² sized FEP $\mu $ LEDs presumably due to the detection limit.

In the reverse bias condition of FEP $\mu $ LEDs, an increase of leakage current could be observed as the positive $V_{G}$ increases both in $100\times 100~\mu $ m² and $10\times 10~\mu $ m² sized devices. However, no variation in current density could be observed under negative $V_{G}$ for both devices.

Fig. 2(c-d) illustrates the $V_{G}$ -dependent EQE-current density characteristics of FEP $\mu $ LEDs with different sizes of $100\times 100~\mu $ m² and $10\times 10~\mu $ m². The $100\times 100~\mu $ m² shows negligible change in EQE under both positive and negative $V_{G}$ . For the $10\times 10~\mu $ m² FEP $\mu $ LEDs, the effect of $V_{G}$ is significant, particularly in the low current density region. As positive gate bias is applied, the EQE at the low current density region decreases. Specifically, the EQE at 1 A/cm2 decreases approximately from 0.45% ($V_{G}{=}0$ V) to 0.12% ($V_{G}{=}4$ V), and when positive $V_{G}$ is applied, EQE is increased to 1.39% ($V_{G}{=} -4$ V) at 1 A/cm² showing a three-fold increase. However, controlled $V_{G}$ does not affect the EQE value in the high current density region above approximately $5\times 10^{1}$ A/cm², where Auger recombination is expected to be dominant.

Furthermore, the maximum EQE and $J_{max. EQE}$ can be controlled with $V_{G}$ where maximum EQE is increased from 2.34% at 33.58 A/cm${^{{2}}}~(V_{G}{=}0$ V) to 2.44% at 24.28 A/cm${^{{2}}}~(V_{G}{=} -4$ V), and in the opposite gate bias, can be decreased to 2.28% at 43.88 A/cm${^{{2}}}~(V_{G}{=}4$ V). Minimal variation in electroluminescence peak wavelength was observed in $10\times 10~\mu $ m² sized FEP $\mu $ LEDs as shown in Fig. 3(a), indicating that the FEP effect has less effect on the light emission properties, which is consistent with the understanding that gate bias does not inject current into the FEP $\mu $ LEDs, and any associated joule heating.

FIGURE 2.

Current density-voltage characteristics under different $V_{G}$ of FEP $\mu $ LEDs with sizes of (a) $100\times 100~\mu $ m² and (b) $10\times 10~\mu $ m². EQE-current density characteristics under different $V_{G}$ of FEP $\mu $ LEDs with sizes of (c) $100\times 100~\mu $ m² and (d) $10\times 10~\mu $ m².

FIGURE 3.

(a) Electroluminescence peak wavelength of devices with a size of $10\times 10~\mu $ m² (b) Enhancement ratio of FEP $\mu $ LEDs under positive and negative $V_{G}$ .

To quantify the size-dependent effect of gate biasing, the enhancement ratio (E.R) at 1A/cm² has been calculated under Eq. (1) and is plotted in Fig. 3(b):\begin{equation*} E.R = \frac {{EQE}_{V_{G}} - {EQE}_{V_{G}\left ({{ 0V }}\right)}}{{EQE}_{V_{G}\left ({{ 0V }}\right)}} \tag {1}\end{equation*}

As shown in Fig. 3(b), No observable enhancement or degradation is evident in FEP $\mu $ LEDs with dimension exceeding $40\times 40~\mu $ m². However, for devices with dimensions smaller than $40\times 40~\mu $ m², the gate effect becomes increasingly pronounced. This observation suggests that size-dependent efficiency degradation begins to influence performance at dimensions near or below $40\times 40~\mu $ m² in GaN-based blue $\mu $ LEDs, a trend consistent with previously reported studies [1], [11], [14]. Yet, this trend in enhancement ratio could differ depending on the effectiveness of sidewall trap elimination by the sidewall passivation scheme. The enhancement and degradation effects induced both by positive and negative $V_{G}$ appear to reach saturation with the absolute value of 4V. Considering the gate oxide thickness of 50 nm and the applied voltage bias range, the maximum possible electric field across the oxide is estimated at 0.8 MV/cm, even if the entire $V_{G}$ is applied to the oxide. This field is significantly below the threshold required to induce a conductive channel, as per classical MOS device theory [15], [16]. Therefore, the observed saturation behavior of EQE is unlikely to be driven by depletion or inversion mechanisms typically observed in classical MOS structures.

Rather, the observed phenomenon of the gate effect can be interpreted as the effect of the de-trapping and trapping process of electrons from the electron traps, as illustrated in Fig. 4.

FIGURE 4.

Schematic of electron (a) de-trapping and (b) trapping.

When negative $V_{G}$ is applied at the sidewall, the relative position of the conduction/valence band $(E_{C}/E_{V})$ and the fermi level $(E_{F})$ of InGaN near the Al₂O₃/InGaN interface decreases, while the surface states maintain the same level. This leads to the gradual de-trapping of electrons from the electron traps as the absolute value of negative $V_{G}$ increases as illustrated in Fig. 4(a). As the de-trapping process of electrons precedes, the surface recombination in the sidewall decreases, evidenced by the increase of EQE at low current densities and the maximum EQE. Additionally, the observed decrease in the current density near the turn-on voltage implies the decrease of the surface recombination current, since the surface recombination is associated with the net flow of carriers to the surface [17].

In the opposite scenario, where positive $V_{G}$ is applied, electron trapping can occur at the electron trap sites. With this trap occupied, an increase in surface recombination and the corresponding current can be observed as depicted in Fig. 2(a) and (c). This highlights that to effectively address size-dependent efficiency degradation, passivation schemes that effectively reduce the densities of the electron trap or strategies that inhibit electron migration or capture at the electron traps must be considered.

The observed phenomenon and the interpretation regarding the phenomenon show consistency with the previous research. Recent studies have suggested that the dry etching process increases electron trap densities of E_C −0.7eV (for GaN quantum barriers) and/or $E_{C} -1.0$ eV (for blue InGaN quantum wells), as well as the increase of hole trap densities of near $E_{V} {+} 0.75$ eV [8], [9]. These traps contribute to efficiency degradation as device sizes are reduced. While electron traps are effective nonradiative recombination centers, hole traps, though inefficient as nonradiative recombination centers due to the slow electron capture rate [18], are responsible for increased tunneling and carrier leakage. Under the consideration that the electron traps are the dominant non-radiative recombination centers, the effect of de-trapping and trapping of electrons from the electron trap through the FEP $\mu $ LEDs, and its effect on the EQE at low current densities confirms that control of both electrons and electron traps are required to solve the size-effect.

SECTION IV. Conclusion

In conclusion, FEP $\mu $ LEDs have been demonstrated by adopting an MOS gate in the sidewall of GaN-based blue $\mu $ LEDs. The gate effect can actively control the surface band bending of $\mu $ LEDs in the sidewall. The positive $V_{G}$ -induced electron trapping led to an increase of surface recombination confirmed by a decrease of EQE from 0.45% ($V_{G}{=}0$ V) to 0.12% ($V_{G}{=}4$ V) at 1 A/cm² and increase of $J_{max. EQE}$ , while negative $V_{G}$ -induced electron de-trapping from the electron trap led to increase of EQE to 1.39% ($V_{G}{=} -4$ V) at 1A/cm² and a reduction of $J_{max. EQE}$ in a $10\times 10~\mu $ m² sized FEP $\mu $ LED. These results indicate proper sidewall passivation to reduce the trap densities of electron trap or strategies to inhibit the migration of electron to be captured by traps must be considered to address the size-dependent efficiency degradation of $\mu $ LEDs to achieve efficient ultrahigh resolution display.