Application-Specific System-On-Chip Design for Advanced Encryption Standard Cryptography Algorithm

This paper concentrates on the development of System-On-Chip for the Advanced Encryption Standard algorithm. This method includes the transformation of plaintext into cipher text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The SOC design for the encryption of the AES depends on the synthesizable HDL code development for all 10 rounds of processes with the key expansion algorithm. The LUTs are used for the S-box in the HDL code. The proposed SOC is designed using the Cadence EDA tools by making use of the synthesized HDL code for the proposed methods and analyzed for the VLSI parameters

I. Introduction

Data Security plays a pivotal role in many real-time applications such as banking authentication, online services, identity checks, and sensing technology. Cryptography is the process of hiding original data in another format and is retrieved by using the concept of Key. In general, there are several types of cryptography algorithms namely DES, AES, RSA, and ECC etc. Among these algorithms, the AES is predominately used because it is highly secure, easy to design, and faster in operation. AES is six times faster than triple DES. Key Length that can be used for AES is 128 – Bits, 192 – Bits and 256- bits, whereas in DES the Key length is 56 – Bits.