N-Well Patterning of P-Type CMOS Substrate for Improving Quality Factor of on-Chip Inductors at Millimeter Wave Frequencies

This paper proposes a technique for the improvement of quality factor $(Q)$ of on-chip spiral inductors through n-well patterning on a p-type low resistive substrate in a typical bulk CMOS process. Two styles of patterning structures are designed to reduce the loss due to eddy currents and capacitively coupled currents in on-chip inductors. The advantage of this proposed techniques is that they do not degrade the self-resonant frequency of the inductor, unlike other patterned ground shielding techniques. The measured results of the proposed techniques are compared with that of a spiral inductor without such patterning for their quality factor and inductance. For an 120 pH octagonal single-turn spiral inductor, in the millimeter wave frequency range, the first structure shows a 77% improvement in $Q$, whereas the second structure shows a 16% improvement. Inductance is increased by 8 % and 4 % for the first and second structures, respectively.

I. Introduction

In recent times, millimeter-wave (mm-wave) frequencies have gained more interest for offering the advantages like high data rates, compact designs, large bandwidths, etc. Meanwhile, lower GHz frequencies face congestion due to heavy use. These frequency ranges are utilized in 5G and 6G communication [1], [2], non-destructive testing [3], medical imaging [4], astronomy [5] and more. At these high frequencies, on-chip inductors are critical in CMOS Radio Frequency Integrated Circuit (RFIC) design. The inductors are essential and critical elements in numerous circuits such as voltage controlled oscil-lators, low noise amplifiers, power amplifiers, phase shifters, mixers and more [6]–[12].