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Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling | IEEE Conference Publication | IEEE Xplore

Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling


Abstract:

In this work, we provide a methodology for designing an anti-ferroelectric(AFE) based FRAM cell capacitor that operates at low voltage (\leq 1 V), while achieving super...Show More

Abstract:

In this work, we provide a methodology for designing an anti-ferroelectric(AFE) based FRAM cell capacitor that operates at low voltage (\leq 1 V), while achieving superior high and steep polarization (\Delta \mathrm{P}) switching characteristics (23.5 µC/cm2), considering BEOL compatibility (process temp. \leq 400 °C). Furthermore, through experimental demonstration and modeling, we validate that the steep \Delta \mathrm{F} switching, closely related to the domain size of the AFE material, is a key enabler for mitigating disturbance issues in 1T-nC FRAM arrays. Our reliable model framework, calibrated with physical and structural parameters, determines the optimal number of stacks for the 3D 1T-nC FRAM architecture from the perspective of disturbance characteristics. This work highlights the potential of hafnia-based materials in embedded cache memory, bridging the gap between \Delta P functionality and reliability.
Date of Conference: 07-11 December 2024
Date Added to IEEE Xplore: 18 February 2025
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Conference Location: San Francisco, CA, USA

I. Introduction

Today, research efforts are focused on realizing large bandwidth computing systems through the use of additional process units [1], and the development of various embedded memories (EM) [2]. Among these, hafnia-based 1T-nC FRAM is proposed as a viable candidate for next-generation EM in advanced computing systems due to its high density and fast operation speed [3]–[5]. However, the integration of EM with logic devices limits the total height of EM because of cointegrated interconnections (Fig. 1) [6]. Specifically, the interconnection metal lines in logic circuits hinder the increase in the area (height) of cell capacitors for embedded DRAM, a representative EM, posing a significant obstacle for future technology development (Fig. 2(a)). In this regard, hafnia ferroelectric (FE) material offers a promising solution by providing a high property, which can overcome this limitation (Fig. 2(b)) [3]–[5]. Additionally, the non-volatile can significantly reduce the standby energy loss of typical EM [7].

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