Loading [a11y]/accessibility-menu.js
ChiPICA: Chiplet Physical Inspection Certification Authority for Trust Verification in Heterogeneous Integration | IEEE Conference Publication | IEEE Xplore

ChiPICA: Chiplet Physical Inspection Certification Authority for Trust Verification in Heterogeneous Integration


Abstract:

Heterogeneous Integration (HI) of chiplets offers diverse functionalities and enhanced performance within compact packaging by assembling chiplets sourced from different ...Show More

Abstract:

Heterogeneous Integration (HI) of chiplets offers diverse functionalities and enhanced performance within compact packaging by assembling chiplets sourced from different foundries into one substrate via 2.5D/3D advanced packaging techniques. However, an adversarial foundry, with complete access to the chiplet layout and test vectors, could maliciously modify the design with hardware Trojans, compromising the security of the System-in-Package (SiP). In this paper, we introduce the Chiplet Physical Inspection Certification Authority (ChiPICA) to ensure the trustworthiness of chiplets by validating Scanning Electron Microscopy (SEM) images of the chiplet’s backside against the layout of the active layer on individual logic cells using Fourier Shape Descriptor-based shape matching. Additionally, the proposed framework only requires the design house to provide shape descriptor values for individual logic cells in the form of a shape packet list, which protects the intellectual property of the chiplet designer. A fast verification algorithm that operates on the shape packet list, along with a pipelined implementation that achieves an average speed up of approximately 6.5x compared to previous method is also proposed in this paper.
Date of Conference: 12-14 November 2024
Date Added to IEEE Xplore: 16 December 2024
ISBN Information:
Conference Location: Huntsville, AL, USA
No metrics found for this document.

I. Introduction

Technological advancement drives demand for increased computational capacity to run increasingly complex applications, followed by higher transistor density in a single monolithic chip. However, with deceleration in Moore’s Law and Dennard scaling, the semiconductor industry is moving towards heterogeneous integration in which individual silicon modules, known as chiplets or dielets, are integrated and connected into an interposer substrate to form a final package called system-in-package (SiP) [1]. SiP offers low power, high performance and various functionalities in smaller packages [1], [2]. Chiplets can be collected by SiP integrators from various sources. They can be fabricated either by an Integrated Device Manufacturer (IDM) or outsourced to an independent foundry by a fabless design company.

Usage
Select a Year
2025

View as

Total usage sinceDec 2024:79
051015202530JanFebMarAprMayJunJulAugSepOctNovDec201226000000000
Year Total:58
Data is updated monthly. Usage includes PDF downloads and HTML views.
Contact IEEE to Subscribe

References

References is not available for this document.