A Low-Noise Current-Squared Delta-Sigma-Modulation Boost Converter Suitable for Low-Voltage Wireless Sensor Networks With Transient-Accelerated Techniques

This paper presents a low-noise current-squared delta-sigma-modulation boost converter suitable for low-voltage wireless sensor networks with transient-accelerated techniques. There are two current-controlled loops and two voltage-controlled loops in the proposed converter to achieve low noise, fast-transient-response times, and low-transient voltages. The converter’s transient-accelerated circuit consists of a current sensing circuit and a dynamic slope compensation circuit, which significantly improves the transient response. Additionally, the converter has low output noise and a fast-transient recovery time, and exhibits good undershoot and overshoot voltage control ability when the load current changes. Experimental results indicate that the boost converter is fabricated using the TSMC T18HVG2 1P6M CMOS process with a chip area of 1.26 mm $\times 1.18$ mm. The sampling frequency of 10 MHz, and the output-to-noise ratio (ONR) is 70.4dB. Furthermore, the converter achieves a peak power efficiency of 88 %, with optimal performance achieved at a load current of 70 mA and an output voltage of 1.8 V.

SECTION I. Introduction

With the rapid development of emerging markets such as 5G wireless communication technology, artificial intelligence (AI), Internet of Things (IoT), and electric vehicles, there has been an increase in product variety and job opportunities. In this market environment, the requirements for power supply quality have become increasingly stringent. Nowadays, when designing power management integrated circuits (PMICs), in addition to considering specifications such as size, response speed, stability, and conversion efficiency, special attention also needs to be given to the issue of electromagnetic interference (EMI), especially in systems applications that are highly sensitive to noise, such as low-voltage wireless sensor networks and radio frequency (RF) circuits. Therefore, to meet the demands of modern electronic products, designing PMICs with high conversion efficiency and low EMI has become an important goal in designing power management solutions [1].

Switching-mode DC-DC converters are widely used because they offer high conversion efficiency and can handle a wide range of load currents. However, traditional boost converters typically use pulse-width modulation (PWM) control with a fixed frequency of operation [2]. In this control method, the switching frequency is determined by an external ramp signal, which simplifies the design and ensures high efficiency. Nevertheless, when examining the output voltage in the frequency domain, one can observe the presence of related harmonics and switching noise at multiples of the switching frequency, leading to electromagnetic interference that may impact downstream applications. Fig. 1 shows the architecture of a PWM boost converter.

FIGURE 1.

The circuit architecture of a PWM boost converter.

To mitigate electromagnetic interference (EMI), frequency hopping spread spectrum (FHSS) is used as one of the methods. It involves spreading the switching frequency over a broader range instead of keeping it fixed. This approach helps to reduce the concentration of spectral peaks within the system bandwidth [3], [4]. However, FHSS may lead to synchronization difficulties between the clock and switching frequency, resulting in duty cycle errors during frequency switching and increased output voltage ripple. In terms of printed circuit board layout, various techniques can be employed to reduce EMI, including optimizing component placement, routing power and signal lines, and implementing grounding strategies.

In recent years, the delta-sigma-modulation architecture has been applied to DC-DC converters. Fig. 2 shows a boost converter using the delta-sigma-modulation, which leverages oversampling theory and noise shaping techniques to minimize EMI in the output signal. This architecture is divided into discrete time and continuous time sections. The traditional approach uses discrete-time delta-sigma-modulation with a switched capacitor circuit, which introduces delay and phase issues in the internal integrator. To avoid harmonic distortion caused by insufficient slope or bandwidth, the bandwidth design must be at least four times the clock frequency [5], [6], [7]. On the other hand, continuous-time delta-sigma-modulation can reduce the gain-bandwidth product of the amplifier and overall power consumption, with lower delay compared to the discrete-time approach. However, due to overall loop issues, the transient response of the converter becomes slower, necessitating compensators to stabilize the entire system [8], [9], [10], [11]. Additionally, increasing the order of the digital sigma-delta modulation can enhance the signal-to-noise ratio (SNR) based on circuit requirements. However, this may also lead to system stability concerns, requiring a trade-off between SNR and system stability in the design.

FIGURE 2.

The boost converter using the delta-sigma-modulation.

Since the wireless sensor networks are sensitive to the noise of supplied voltages, we need low-noise boost converters. This paper proposes a low-noise current-squared delta-sigma-modulation boost converter suitable for low-voltage wireless sensor networks with transient-accelerated techniques. The challenging is the controlled circuit design. To obtain better performance, we use the proposed controlled circuits to design our boost converter. The proposed converter adopts continuous-time delta-sigma-modulation architecture. By using oversampling theory and noise shaping techniques, it reduces EMI in the output spectrum. Furthermore, the dynamic-compensation-controlled circuit improves transient response time and voltage magnitude. The paper introduces the description of the overall circuit in Section II. Measurement results are presented in Section III, and the paper concludes in Section IV.

Our contributions and innovations are as follows: (1) This paper presents a new low-noise current-squared delta-sigma-modulation boost converter with transient-accelerated techniques; (2) The proposed converter have two current-controlled loop and one voltage-controlled loop to increase the phase margin and gain margin of loop gain to achieve fast transient response and low transient voltage; (3) we designed and implemented the proposed chip and measured the experimental results to present in the paper; (4) From comparison table, we can observe that the performance of the proposed converter is better than others’ works.

SECTION II. Circuit Description

The proposed architecture of the second-order delta-sigma modulation boost converter suitable for low-voltage wireless sensor networks with dynamic-compensation-controlled (DCC) techniques is shown in Fig. 3. This structure consists of a voltage-mode delta-sigma-modulation and a dynamic-compensation-controlled circuit. The dynamic-compensation-controlled circuit inputs current to the first-level integrator output of the second-order delta-sigma modulation circuit. By rapidly supplying current through this method to adjust the first-level integrator within the control loop, the transient response of the converter is enhanced, thereby speeding up its transient response. There are two controlled loops in the proposed boost converter. The first one is from the current-sensing circuit, the feedback signal is $I_{sen}$ . The second one is from the dynamic-slope generator, the feedback signal is $I_{x}$ . This approach is referred to as Dynamic-Compensation-Controlled (DCC) techniques in this paper. In our design, the voltage V_duty is used to turned on and turned off the power switched. As the voltage V_duty is high, the M_N is turned on and the M_P is turned off; when the voltage V_duty is low, the M_N is turned off and the M_P is turned on. The converter designed by using delta-sigma modulator is not a fixed-frequency power converter, but a variable-frequency converter, which can spread the energy of the switching frequency to the neighboring frequencies evenly, so there is almost no switching noise of the fixed-frequency, so it is different from the converter designed by the FHSS technology, and the energy of the switching noise will be lower, so the EMI results will be better. The proposed converter mainly comprises the following circuits: Type-III compensator, second-order CT-DSM, Dynamic Slope Compensation circuit, New-Type DCR Current-Sensor circuit, Nonoverlapping circuit, and Driver. Detailed descriptions of each circuit will be provided below.

FIGURE 3.

The proposed converter.

A. Compensator

In this paper, the proposed converter utilizes a Type-III compensator, as depicted in Fig. 4(a) [12]. This circuit is composed of an operational amplifier (OPA) and passive components arranged in series and parallel configurations. The bode diagram of the compensator is shown in Fig. 4(b). Notably, the compensator incorporates three poles and two zeros. The zero-frequency pole is used to boost the low-frequency gain, while the two zeros contribute to achieving a phase boost of up to 180° and control the bandwidth by means of the two high-frequency poles, effectively suppressing high-frequency noise. Through careful design of the pole and zero placements, the phase boundary, DC gain, and unity-gain frequency of the circuit can be optimized, thereby enhancing the overall stability of the entire circuit system.

FIGURE 4.

(a) Circuit diagram (b) Bode plot of the type-III compensator.

The transfer function of the Type-III compensator is represented by equation (1), and the positions of the poles and zeros can be analyzed using equations (2), (3), and (4). Since a power converter with a second order delta-sigma modulator is a very complex system, so it is difficult to analyze the stability of the circuit with equations, so we use SIMPLIS and HSPICE to simulate the circuit and verify the stability of the proposed converter. Since the boost converter has a zero point in the right half plane, therefore, we use a Type-III compensator to compensate the stability of the circuit. The values of compensation network are R$_{1}= 50\Omega$ , R$_{2}=20$ k$\Omega$ , R$_{3}=10$ k$\Omega$ , R$_{4}=25$ k$\Omega$ , C$_{1}=750$ pF, C$_{2}=5$ pF, C$_{3}=150$ pF.

$$\begin{align*} & \left |{{ \frac {V_{c}(S)}{V_{out}(S)} }}\right | \\ & =\frac {\left ({{ 1\!+\!S\cdot R_{4}\cdot C_{3} }}\right )\left [{{ 1\!+\!S\cdot \left ({{ R_{2}\!+\!R_{1} }}\right ){\cdot C}_{1} }}\right ]}{S\cdot R_{2}\left ({{ C_{2}\!+\!C_{3} }}\right )\left ({{ 1\!+\!S\cdot R_{4}\cdot \frac {C_{2}\cdot C_{3}}{C_{2}+C_{3}} }}\right )(1\!+\!S\cdot R_{1}\cdot C_{1})} \tag {1}\\ \left |{{ f_{z1} }}\right |& =\frac {1}{2\pi \cdot R_{4}\cdot C_{3}},\left |{{ f_{z2} }}\right |=\frac {1}{2\pi \cdot \left ({{ R_{2}+R_{1} }}\right ){\cdot C}_{1}} \\ & \approx \frac {1}{{2\pi \cdot R}_{2}{\cdot C}_{1}};R_{2}\gg R_{1} \tag {2}\\ \left |{{ f_{p0} }}\right |& =\frac {1}{{2\pi \cdot R}_{2}\cdot C_{3}}\approx 0,\left |{{ f_{p1} }}\right |=\frac {1}{2\pi \cdot R_{4}\cdot \frac {C_{2}\cdot C_{3}}{C_{2}+C_{3}}} \\ & \approx \frac {1}{{2\pi \cdot R}_{4}{\cdot C}_{2}};C_{3}\gg C_{2} \tag {3}\\ \left |{{ f_{p2} }}\right |& =\frac {1}{{2\pi \cdot R}_{1}{\cdot C}_{1}} \tag {4}\end{align*}$$

B. Second-Order CT-DSM

Fig. 5 depicts the block diagram of a second-order Continuous-Time Delta-Sigma Modulator (CT-DSM), composed of two integrators, a quantizer, and a one-bit digital-to-analog converter (DAC). Each integrator is constructed using a rail-to-rail OTA and an output capacitor. The circuit operates by passing the input analog signal through two stages of integration, followed by quantization by the quantizer to convert the input analog signal into a digital signal for output. Simultaneously, the digital-to-analog converter converts the feedback signal into an analog signal, which is then fed back to the input terminal to complete the feedback loop. Fig. 6(a) displays simulation waveforms of the second-order CT-DSM. The signal V_C inputs a sinusoidal waveform into the second-order CT-DSM, where V_cout1 and V_cout2 represent the output waveforms of the first and second stage integrators, respectively, while simultaneously tracking changes in the input signal. Finally, the quantizer outputs the V_duty signal, which is further processed through a nonoverlapping circuit and a driver to generate a non-fixed frequency signal controlling the power transistor switches. Fig. 6(b) represents the spectrogram of the output from the second-order CT-DSM, demonstrating the noise shaping characteristic of approximately 40dB per decade in the circuit.

FIGURE 5.

Block diagram of the second-order CT-DSM.

FIGURE 6.

(a) Simulation waveforms (b) Output spectrogram of the second-order CT-DSM.

1) Integrator

Fig. 7 displays the circuit diagram of the proposed rail-to-rail operational transconductance amplifier (OTA). This amplifier is applied in the delta-sigma modulation, and the circuit architecture includes a bias circuit, an N-type OTA, a P-type OTA, and an output capacitor to form an integrator circuit. Using the rail-to-rail OTA provides a wider input voltage operating range compared to using only N-type or P-type OTAs based on the input voltage range. When only the N-type differential pair is conducting, the input common mode voltage (V$_{\mathrm {CM}}$ ) is within V$_{\mathrm {OV8}}+$ V$_{\mathrm {GS1}} \le$ V$_{\mathrm {CM}} \le$ V_DD-V_gs3-V_th1. Similarly, when only the P-type differential pair is conducting, the input common mode voltage (V$_{\mathrm {CM}}$ ) is within V$_{\mathrm {GS12}}+$ V$_{\mathrm {TH10}} \le$ V$_{\mathrm {CM}} \le$ V_DD-$\vert$ V$_{\mathrm {OV17}}\vert$ -$\vert$ V$_{\mathrm {GS10}}\vert$ . If the common mode input voltage falls outside these two conditions, both the N-type and P-type differential pairs will conduct. As a result, when the output signal of the digital-to-analog converter (DAC) is fed back to the rail-to-rail OTA, there is a wider range of voltage variations. Let’s use the first-stage integrator to explain its operating principle. When the sensed voltage passes through the OTA, it is converted into a current signal, I_cout1, which charges or discharges the capacitor, C₁. The direction of charging or discharging C₁ depends on the comparison of the two input voltages, V_c and V_a. Specifically, when V_c is higher than V_a, I_cout1 charges C₁; conversely, when V_c is lower than V_a, I_cout1 discharges C₁. In any case, the integrated voltage, V_cout1, is obtained by integrating I_cout1 with respect to C₁. The equation of the circuit can be expressed as (5)–(7).

$$\begin{align*} G_{M}& =G_{M(N)}+G_{M(P)}=g_{m2}\times \frac {g_{m6}}{g_{m5}}+g_{m10}\times \frac {g_{m13}}{g_{m12}} \tag {5}\\ I_{cout1}& =\left ({{ V_{c}-V_{a} }}\right )\times G_{M} \tag {6}\\ V_{cout1}& =\frac {1}{C_{1}}\int {I_{cout1}dt} \tag {7}\end{align*}$$

FIGURE 7.

Rail-to-Rail OTA circuit.

2) One-Bit Quantizer

As shown in Fig. 8, a one-bit quantizer is composed of a Dynamic Comparator and an SR-Latch. The circuit operates in two modes: Hold Mode and Compare Mode, which are selected based on the voltage level of V_clk. In the Hold Mode, when V_clk is at a low voltage, the transistors (M_p1, M$_{\mathrm {p2}}$ ) are turned on, while (M_n1, M$_{\mathrm {n2}}$ ) are turned off. As a result, the voltages at points A and B are pulled high, and the inverter outputs a low signal. This keeps the SR-Latch output signal (Q) in its previous state. On the other hand, in the Compare Mode, when V_clk is at a high voltage, the transistors (M_p1, M$_{\mathrm {p2}}$ ) are turned off, and (M_n1, M$_{\mathrm {n2}}$ ) are turned on. Then, the input signals (V$_{\mathrm {inn}}$ ) and (V$_{\mathrm {inp}}$ ) are compared to determine the conduction state of the transistors (M_n5, M$_{\mathrm {n6}}$ ). The voltages at points A and B are determined through a positive feedback loop composed of transistors (M_n3, M_n4, M_p3, M$_{\mathrm {p4}}$ ). Finally, the SR-Latch outputs the signal (Q) accordingly.

FIGURE 8.

One-bit quantizer circuit.

C. Dynamic-Compensation-Controlled Techniques

This paper proposes a dynamic-compensation-controlled technique to improve the transient response of the converter. It consists of a dynamic slope compensation circuit and a new-type DCR current-sensor circuit. Fig. 9 shows the dynamic-compensation-controlled circuit. The following will introduce the working principles and simulation results of these circuits.

FIGURE 9.

Dynamic-compensation-controlled circuit.

The dynamic slope compensation circuit is shown in Fig. 9. The feedback signal V_fb obtained by dividing the output voltage V_out through a voltage divider resistor is connected to the positive terminal of the first operational amplifier. By utilizing the negative feedback virtual short-circuit characteristic of the operational amplifier, the feedback signal is converted into a current I_R1 through a resistor R₁. The current is replicated as I_Mp2 by the current mirror composed of transistors M_p1 and M_p2 to charge the capacitor C₁ as shown in equation (8). The capacitor C₁ discharges through the control of the signal V_n that controls the action of the transistor M_n2 in the discharge path, producing a sawtooth wave signal V_C1 as shown in equation (9). The V_C1 signal is converted into a current I_R2 by the resistor R₂ and then replicated as I_x K times by the current mirror composed of transistors M_p3 and M_p4 to generate a current output as shown in equation (9). Because the path for converting currents I_x and I_sen to V_cout1 is relatively short, the purpose of this is to accelerate the responsiveness of the fast converter during load changes. Since using the feedback voltage V_FB to generate the slope signal can improve the phase margin and gain margin, we used it to design our converter.

$$\begin{align*} V_{fb}\left ({{ t }}\right )& =\frac {1}{2}V_{out}\left ({{ t }}\right ),~I_{R1}\left ({{ t }}\right )=\frac {V_{fb}\left ({{ t }}\right )}{R_{1}}, \\ {I}_{Mp2}(t)& =K\times \frac {V_{fb}\left ({{ t }}\right )}{R_{1}} \tag {8}\\ V_{C1}\left ({{ t }}\right )& =\frac {K}{C_{1}R_{1}}\int {V_{fb}\left ({{ t }}\right )} dt,~I_{R2}\left ({{ t }}\right )=\frac {V_{C1}\left ({{ t }}\right )}{R_{2}}, \\ {I}_{x}(t)& =K\times \frac {V_{C1}\left ({{ t }}\right )}{R_{2}} \tag {9}\end{align*}$$

Fig. 10 illustrates the circuit diagrams of the conventional DCR current-sensor circuit and the new-type DCR current-sensor circuit. The difference lies in the replacement of the resistance of the RC network with the parallel connection of transistors M_psw and M_nsw. When the transistors are operating in the linear region, they can function as linear resistors. The resistance value R_DS is expressed in equations (10) and (11), and the transistor size is designed to satisfy equation (12), which can obtain the same voltage signal V_csw as the traditional inductance DC resistance current sensing circuit. The V_csw signal is converted into a current I_R3 by the resistor R₃, and then replicated as I_sen K times by the current mirror composed of transistors M_p5 and M_p6 to generate a current output as shown in equation (13). The advantage of this circuit is that it reduces the use of external components and speeds up the detection speed when the circuit changes. The layout area is also smaller than when using resistors. The disadvantage is that the resistance value is not fixed, so there may be accuracy issues.

$$\begin{align*} R_{DS,psw}& =\frac {1}{{\mu }_{p}C_{OX}\frac {W}{L}(V_{GS,psw}-V_{TH,psw})} \tag {10}\\ R_{DS,nsw}& =\frac {1}{{\mu }_{n}C_{OX}\frac {W}{L}(V_{GS,nsw}-V_{TH,nsw})} \tag {11}\\ R_{sw}\times C_{vcsw}& =\frac {L}{R_{DCR}} \tag {12}\\ I_{R3}& =\frac {V_{csw}}{R_{3}}, {I}_{sen}=K\times \frac {V_{csw}}{R_{3}} \tag {13}\end{align*}$$

FIGURE 10.

Illustrates the structural configurations for (a) The conventional DCR Current-Sensor and (b) The New-Type DCR Current-Sensor.

Next, the functionality of the dynamic-compensation-controlled techniques is verified through simulation using HSPICE. Fig. 11 presents the transient simulation results of the converter, showing the transient simulation results of the converter without and with the dynamic-compensation-controlled circuit. From the simulation results, it can be observed that the addition of the dynamic-compensation-controlled circuit improves the transient response time of the voltage-mode continuous-time delta-sigma modulator boost converter. In other words, it enhances the inherently slow transient response characteristics of the voltage-mode continuous-time delta-sigma modulator boost converter. Since the conventional DCR current sensors cause more power consumption, we use new current sensing circuits to replace them. However, in the fact, there is the problem as the reviewer said. Compared to conventional resistors, transistor-based resistors exhibit better tracking capabilities for drift.

FIGURE 11.

The transient simulation results of the converter, comparing the transient behaviors of the converter without and with the dynamic-compensation-controlled circuit.

D. Nonoverlapping Circuit and Driver

In the switched-mode DC-DC converter, in order to improve the overall efficiency of the circuit, diodes are replaced with transistors. The N-type and P-type power transistors are selectively turned on or off based on the duty cycle signal. It is crucial to carefully manage the switching times of these power transistors to avoid simultaneous conduction and potential short-circuiting of the power supply to the ground, which could damage the chips. To address this, the duty cycle signal is first processed through a non-overlapping circuit to stagger the conduction times of the power transistors.

The circuit, as shown in Fig. 12, is composed of digital logic gates such as inverters and NOR gates, combined with delay circuits. By appropriately designing the delay circuits according to the specifications of the circuit, the conduction times of the power transistors can be staggered effectively.

FIGURE 12.

Nonoverlapping circuit.

In general, to achieve a lower on-state resistance (R$_{\mathrm {ON}}$ ), the aspect ratio of power transistors is designed to be very large. However, the large equivalent input capacitance at the gate of power transistors makes driving them difficult. To address this issue, a larger driving current is required to control the switching of power transistors more quickly and accurately. The circuit, as shown in Fig. 13, uses a series of progressively larger inverters to drive the power transistors.

FIGURE 13.

Driver circuit.

SECTION III. Experimental Results

The proposed boost converter suitable for low-voltage wireless sensor networks has been realized using the TSMC T18HVG2 1P6M CMOS process, encompassing a total chip area of 1.487 mm². The IC floorplan and chip micrograph are illustrated in Figs. 14(a) and 14(b). The specifications of the proposed converter are presented in Table 1. This design incorporates a $2.2\mu$ H inductor and a $10\mu$ F capacitor. This design is intended to accommodate input voltage ranging from 1V to 1.4V and efficiently boost it to an output voltage of 1.8V. The load current capacity spans from 10 mA to 100 mA. Additionally, the converter operates at a fixed sampling frequency of 10MHz. The steady-state measurement outcomes of the converter are illustrated in Figs. 15(a) and 15(b). With an input voltage of 1.2V and an output voltage of 1.8V, the load current varies between 10mA and 100mA. The

TABLE 1 Comparisons to State-of-the-Art Delta-Sigma-Modulation Converters

FIGURE 14.

(a) IC floorplan (b) Chip micrograph.

FIGURE 15.

Displays the measurement outcomes for I_LOAD and V_OUT under the conditions of V$_{\text {IN}} =1.2$ V and V$_{\text {OUT}} =1.8$ V, specifically illustrating (a) I$_{\text {LOAD}} =10$ mA and (b) I$_{\text {LOAD}} =100$ mA.

figure reveals that the converter operates with a variable switching frequency and maintains a ripple voltage below 11mV. Continuing with the measurements, we examined the converter’s transient response. Fig. 16 illustrates the transient behavior of the converter without the implementation of the dynamic-compensation-controlled circuit. The observed transient times for the converter to transition from light load to heavy load and vice versa were $70\mu$ s and $62\mu$ s, respectively. During these transitions, the transient voltages recorded were 28mV and 39mV. In contrast, Fig. 17 showcases the measured transient responses of the converter when employing the dynamic-compensation-controlled circuit. In this scenario, the converter exhibited quicker transient times, taking $10\mu$ s to shift from light load to heavy load and $11\mu$ s to transition from heavy load to light load. Corresponding transient voltages were measured at 12mV and 9mV. By subjecting the output voltage to a Fast Fourier Transform (FFT), the waveform in the time domain was transformed into a frequency spectrum, as depicted in Fig. 18. Evident peaks appeared at 0Hz and 10MHz, representing the spectrum of the output DC voltage and the sampling frequency, respectively. The spike at 10MHz is commonly referred to as peak noise. To assess the converter’s ability to mitigate noise, we introduced a parameter called the Output-to-Noise Ratio (ONR). This parameter quantifies the range in the frequency spectrum from 0Hz (DC level) to 10MHz (sampling frequency). As indicated in Fig. 18, the calculated ONR value stood at 70.4dB. In Fig. 19, the line chart illustrates the measured efficiency, showcasing that the converter achieves its peak efficiency of 88% when operating at an output voltage of 1.8V and a load current of 70 mA. Table 1 presents a comprehensive comparison of the key performance metrics between this study and other literature. Below the table, you can find the definition of the Figure of Merit (FOM), which serves as an important indicator for evaluating converter performance. A higher FOM value typically signifies superior converter performance. Notably, the proposed converter outperforms the majority of other converters in terms of transient response, efficiency, and FOM.

FIGURE 16.

Measurement of the converter without the dynamic-compensation-controlled circuit, at (a) 10 mA-100 mA and (b) 100 mA-10 mA.

FIGURE 17.

Measurement of the converter with the dynamic-compensation-controlled circuit, at (a) 10 mA-100 mA and (b) 100 mA-10 mA.

FIGURE 18.

Displays the spectrum measurement results of the output voltage.

FIGURE 19.

Line chart illustrates the measured efficiency.

SECTION IV. Conclusion

This paper presents a low-noise current-squared delta-sigma-modulation boost converter suitable for low-voltage wireless sensor networks with transient-accelerated techniques. There are two current-controlled loops and two voltage-controlled loops in the proposed converter to achieve low noise, fast-transient-response times, and low-transient voltages. The utilization of a second-order DSM enables remarkable noise resistance, as indicated by an ONR of 70.4dB. The dynamic-compensation-controlled techniques are strategically employed to enhance the transient response of the converter, thereby addressing the inherent sluggish transient characteristics observed in current-mode DSM boost converters. The proposed converter has been meticulously designed and manufactured using the TSMC T18HVG2 1P6M CMOS process, capable of accommodating input voltages within the range of 1V to 1.4V, achieving voltage boosting functionality, and providing an output voltage of 1.8V. Notably, when subjected to load transitions between 10mA-100mA and 100mA-10mA, the converter achieves transient times of $10\mu$ s and $11\mu$ s, respectively, achieving a peak efficiency of 88%. The superior transient response and potential for reducing electromagnetic interference make the proposed converter well-suited for applications involving noise-sensitive circuits and high-speed operations.