EMSim+: Accelerating Electromagnetic Security Evaluation With Generative Adversarial Network and Transfer Learning

Electromagnetic side-channel analysis (EM SCA) attack poses a serious threat to integrated circuits (ICs), necessitating timely vulnerability detection before deployment to enhance EM side-channel security. Various EM simulation methods have emerged for analyzing EM side-channel leakage, providing sufficiently accurate results. However, these simulator-based methods still face two principal challenges in the design process of high security chips. Firstly, the large volume of measurement data required for a single security evaluation results in substantial time overhead. Secondly, design iterations lead to repetitive security evaluations, thus increasing the evaluation cost. In this paper, we propose EMSim+ which includes two efficient and accurate layout-level EM side-channel leakage evaluation frameworks named EMSim+GAN and EMSim+GAN+TL to mitigate the above challenges, respectively. EMSim+GAN integrates a Generative Adversarial Network (GAN) model that utilizes the chip’s cell current and power grid information to predict EM emanations quickly. EMSim+GAN+TL further incorporates transfer learning (TL) within the framework, leveraging the experience of existing designs to reduce the training datasets for new designs and achieve the target accuracy. We compare the simulation results of EMSim+ with the state-of-the-art EM simulation tool, EMSim as well as silicon measurements. Experimental results not only prove the high efficiency and high simulation accuracy of EMSim+, but also verify its generalization ability across different designs and technology nodes.

I. Introduction

Over the past two decades, side-channel analysis (SCA) attacks have posed a serious threat to the information security of integrated circuits (ICs) [1]. Through the collection and analysis of information inadvertently emitted by ICs, such as electromagnetic (EM) emanations, power consumption, and timing deviations, SCA attacks can compromise the confidentiality of targeted ICs, leading to the leakage of cryptographic chip keys or neural network model parameters [2]. Given these risks, it is necessary to assess the side-channel security of ICs before deployment. Typically, security evaluations happen after the chip fabrication. Failing to meet security standards incurs expensive revision costs and delays time-to-market. Therefore, it is highly desirable to implement side-channel evaluations at the early design stage, allowing designers to identify and modify security vulnerabilities with more flexibility [3].