Understanding Synthesizable Design Methodologies for Mixed-Signal SAR ADC Circuits

The rapid growth of Internet-of-Things (IoT) applications necessitates the development of cost-effective solutions and accelerated design cycles. While digital circuit design has witnessed significant automation, analog design still heavily relies on experienced engineers. To bridge this gap, synthesizable solutions that integrate digital and analog design automation are crucial for efficient IoT development. This paper explores the historical context and current challenges in circuit automation and electronic design automation (EDA) tools, specifically focusing on analog and mixed-signal circuits. As successive approximation register (SAR) ADCs play a critical role in IoT applications, it is important to critically examines the state-of-the-art synthesizable SAR ADCs, discussing the strengths and limitations of different design techniques for various circuit blocks. These findings provide valuable insights for researchers and industry practitioners, informing future research directions in the field of synthesizable SAR ADC design automation.

SECTION I. Introduction

As Internet-of-Things (IoT) applications continue to reshape our world by integrating diverse sensors into powerful system-on-chip (SoC) architectures, the need for rapid design cycles and cost-effective solutions becomes paramount [1]. To embrace the tremendous potential of IoT and facilitate seamless SoC development, the progress of circuit automation and electronic design automation (EDA) tools requires a significant leap forward [1]. By delving into the historical context, it is evident that while digital circuit design has witnessed remarkable automation through commercial electronic design automation (EDA) tools, analog and mixed-signal circuits still heavily rely on the expertise of experienced engineers for schematic and layout designs. However, tools like Berkeley Analog Generator (BAG) [2], BAG2 [3] and MAGICAL [4] have made strides in automating AMS design, supporting the automatic synthesis of circuits like SAR-ADCs. These tools offer a more designer-friendly approach, streamlining design iterations, and promoting process portability.

The future holds promise as circuit automation and EDA tools advance, facilitating the integration of synthesizable solutions that bridge the gap between digital and analog design automation. This integration accelerates IoT development, reduces skyrocketing development costs, and design cycles, and enables cost-effective implementation of mixed-signal circuits. Notably, successive approximation register (SAR) ADCs play a crucial role in achieving accurate and efficient data conversion in IoT applications. Both academia and industry (Fig. 1) have made significant contributions to pushing the performance limit of SAR ADCs in terms of resolution, sampling frequency, and energy efficiency [5], [6]. Developing synthesizable design automation for SAR ADC's analog circuits remains a challenge, including capacitive DAC, sampling switches, and comparator.”

Figure 1.

The performance of data converters published between 1997 and 2023in ISSCC and VLSI conferences (data courtesy of [5]).

Despite the existence of synthesizable design automation techniques for SAR ADCs, the current research landscape lacks a comprehensive overview that compares the efficacy of various circuit implementation techniques. This paper seeks to address this gap by presenting a meticulous summary and design methodologies for SAR ADCs, drawing from recent publications (Section II). Moreover, Section III critically examines the state-of-the-art synthesizable SAR ADCs, highlighting the strengths and limitations of each design technique for different circuit blocks. Section IV concludes our work by providing valuable insights and delineating future research avenues in this domain.

SECTION II. Synthesizable Analog and Mixed-Signal (AMS) Design Methodologies: A Review and Analysis

To comprehend the different types of synthesizable analog and mixed-signal (AMS) design methodologies, to the best of our knowledge, we have searched and included all the related publications from important resources like IEEE, ScienceDirect, Google Scholar, and PubMed. As shown in Fig. 2, although there are slightly more than 100 related papers, there is an increasing trend in this research direction. Prior works have adopted synthesizable solutions using standard cells to implement time-to-digital converters (TDCs) [7], phase-locked loops (PLLs) [8], delay-locked loops (DLLs) [9], low-dropout (LDO) regulators [10], transmitter [11], VCO-Based ADCs [12], and time-domain D/A converters (DACs) [13] as it is much easier to manipulate the signal in the time domain. However, it remains a challenge to develop high-performance voltage domain ADC using foundry-provided standard cell libraries.

Figure 2.

Publications trend in synthesizable mixed-signal circuits.

A. Design Methodology & Framework

As shown in Fig. 3, we can classify the synthesizable circuit design automation into two phases: (i) front-end synthesis and (ii) back-end implementation. It involves a mixture of top-down and bottom-up design methodologies. In the front-end synthesis, the top-down design method translates the design specifications and assigns design constraints to each circuit block. The circuit optimization technique in the bottom-up design method for each circuit block is highly dependent on the type of physical implementation design methodology.

Figure 3.

Agile design methodology of mixed-signal circuit.

B. Circuit Optimization Methods

Library-based & Template-based Methods [14], [15] are considered laborious yet straightforward methods for the implementation of mixed-signal circuits. In the library-based method, the circuit and its corresponding layouts are manually designed beforehand and placed together in a library. This method produces a highly optimized circuit but requires a long design cycle. Furthermore, a large design effort is required to create a new library for each circuit in each technology. These methods are considered suitable for repeatable circuits, such as switches, capacitive/resistive DAC arrays, and so on. It can reduce design efforts and make it easier to be implemented with simple scripting programming.

Knowledge-based methods encodes specific heuristic design knowledge from experts into a design plan that is used during the synthesis of the analog circuit [16]. Specification inputs will be translated to the topology selection and the unique solution of the circuit sizing following the design plan. However, a content-independent design plan is difficult to make, which limits the use of this approach.

Equation-based methods uses a simplified analytic equation to formulate the performance of the circuit [17], [18]. Constrained optimization algorithms instead of a specific design plan are performed using these equations for the optimization of the circuit. Although this approach is more general, the accuracy of the result is a big problem, especially in an advanced process because the design equation has to be derived and simplified so that the optimization algorithm can be executed. To obtain higher accuracy, a full-SPICE simulation-based approach is introduced in the optimization loop.

Machine-learning (ML) & Deep-learning (DL) methods use the idea of evolution to automate the synthesis of analog circuits. However, it requires a large amount of well-designed circuits and huge computation resources to train the model. To date, the use of these ML/DL techniques is primarily used in the circuit sizing [19] or topology generation of analog circuits [20].

Simulation-based methods [21], [22] involve using SPICE simulation in the optimization loop to obtain a higher accuracy but it increases the simulation runtime, especially if the search space is not well defined.

C. Back-End Implementation Design Methodology

The back-end implementation involves the digital logic synthesis and physical layout design of the AMS netlist. We can generally categorize three different methods of automating the physical design layout, namely (i) using the customized programming method, using commercial EDA design methodology and tools with (ii) custom-designed cells, and (iii) foundry-provided standard cells [21], [23], [24], [25], [26], [27], [28]. Note that custom-designed standard cells must abide by the same requirements as foundry-supplied standard cells, such as width and height integral multiples, power rail width, and bulk biasing scheme [29]. Each method has its strengths and weaknesses in terms of reusability, flexibility, and complexity. Among these methods, it is more promising to implement mixed-signal circuits with foundry-provided standard cells as it fully takes advantage of technology scaling with process-qualified libraries, and achieves a shorter turn-around time. To realize high-performance mixed-signal circuits, such as operational amplifiers, ADCs, DACs, and so on, many design techniques have been proposed using a mix of foundry-provided standard cell libraries and custom-designed cells with circuit calibration techniques (Fig. 4).

SECTION III. Review of Synthesizable ADC Building Blocks

Fig. 5 illustrates the architecture of a SAR ADC, which consists of a digital-to-analog converter (DAC), sample-and-hold (S/H) circuit, comparator, and SAR control logic. We will review the circuit implementation techniques for each circuit block. Table 1 summarizes the state-of-the-art synthesizable SAR ADC with its architectural selection, circuit implementation, optimization algorithms, and performances. There has been a gradual transition from custom macrocells to foundries providing standard macrocells for the implementation of the SAR ADC. Circuit calibration has been incorporated to improve the dynamic performance of SAR ADC.

TABLE 1 Summary of State-of-the-Arts Synthesizable SAR ADCs

Figure 4.

Design flow of mixed-signal circuit based on custom cells and standard cells.

Figure 5.

Block diagram of SAR ADC.

A. Digital-to-Analog Converter (DAC) Circuit

CDAC circuits can be classified into (1) conventional binary-weighted capacitive array (CBW), (2) conventional binary-weighted split-capacitive array with an attenuation capacitor (BWA), and (3) dual-capacitive array (DCA) [31], [32]. The differences among these architectures are summarized in Table 2. To date, we have only seen the CBW CDAC being implemented through the synthesizable design methodology due to its simplicity.

TABLE 2 Comparison of Different Architectures for 10-Bit SAR ADC

As the standard cell library provided by the foundry contains only transistors, the CDAC can only be developed in layout description language or manually with custom-designed standard cells for use in synthesizable design methodologies. The use of layout description language, such as SKILL in Cadence [33], python in Synopsys Laker [34], design compiler [35], and klayout [36], helps to extract design rules from the process technology file and it allows portability between different technology nodes. The extracted rules like the minimum metal width and spacing are used to generate a pillar-shaped metal-oxide-metal (MOM) unit capacitor (Fig. 6(a)) whose capacitance can be obtained through parasitic extraction. The size of unit capacitance is inversely proportional to kT/C noise and mismatch requirement. Systematic interconnection algorithms [37], [38] can be used to minimize the routing-induced parasitic mismatch.

Figure 6.

Types of Synthesizable DACs: (a) capacitive DAC using custom-designed standard cells, (b) resistive DAC using foundry-provided standard cell.

Prior works [25], [26], [27] have successfully implemented low-resolution SAR ADC using the standard cell library provided by Foundry. J.-E. Park et al. [25] and Z. Xu et al. [26], [27] adopted the resistive DAC (RDAC), where it is implemented with 2$^{N}$ -1 OAI and inverter standard cells with thermometer coded control logic. As shown in Fig. 6(b), the RDAC utilizes the on-resistance of PMOS or NMOS transistors, and the input thermometer code determines the number of transistors turned on. It is useful to use a dynamic element matching (DEM) calibration technique [39] or redundant DAC architecture (non-radix) [40] to linearize and improve the resolution of the DAC.

B. Sample-and-Hold (S/H) Circuit

The bandwidth of the sample-and-hold S/H circuit is determined by an RC constant, where R is the on-resistance (Ron) and it is determined by the size of the sampling switch and C is the given size of the CDAC circuit. In the sub-100 nm CMOS technologies, the supply voltage drops below 1V, making it challenging to design the S/H circuit with the desirable bandwidth and linearity. Bootstrapped S/H circuit provides a small and consistent on-resistance, which can be realized with additional transistors and capacitors for the generation of gate-source voltages (voltage shifting circuit). The circuit optimization of the S/H circuit is simply to perform transistor sizing for the sampling switch so as to achieve the desired bandwidth and linearity. In voltage-shifting circuits, transistors are relatively less critical for optimization so long as voltage boosting can be achieved. Consequently, the template/simulation-based lookup table (LUT) method or knowledge-based method (discussed in Section II-C) can be used to accelerate the optimization of S/H circuit. Due to the leakage problems of transistors, it would be more beneficial to optimize transistors with high threshold voltages (High Vt) for low-speed ADCs.

For the physical layout design, the synthesizable bootstrapped circuit can be realized by foundry-provided standard cells or custom-designed standard cells. Fig. 7 illustrates a synthesizable bootstrapped circuit realized by the standard cells, including inverter cells, power gating transistors, and a decoupling capacitor [21]. Note that the power gating standard cell is a special type of standard cell that is only available in low power design methodology, which is available in sub-90nm PDK [41]. Synthesizable bootstrapped circuits can be implemented by custom-designed standard cells to achieve highly optimized performance. By using this method, the synthesizable ADC can be implemented in older-generation technology, and the bootstrapped circuit can be fine-tuned.

Figure 7.

An example of the S/H circuit, implemented by the standard cells.

C. Synthesizable Comparator

Synthesizable comparator is first being reported in the stochastic flash ADC [42], [43], which made up of NAND3 logic gates (Fig. 8). As both NMOS and PMOS transistors are driven simultaneously, the NAND3-based comparator cannot handle rail-to-rail common mode (CM) voltages above half VDD due to its narrow input CM range above half VDD. Thus, an ADC can provide rail-to-rail input CM range by using both NAND- and NOR-based comparator chains simultaneously.

Figure 8.

Example of NAND&NOR Synthesizable Comparators: (a) gate-level netlist, (b) schematic diagram, and (c) transistor-level of NAND comparator.

The optimization of noise performance involves changing the driving strength of the logic gates to control the input transconductance. Other types of logic gates such as OAI/AOI [25], [44], and XOR/XNOR [45], have been proposed to further improve the comparator performance. For example, it has been reported that the total harmonic distortion (THD) of the SAR ADC has improved from -50 dBc to -70 dBc by replacing the NAND logic with OAI logic [25]. However, it is still difficult to fine-tune the noise performance of the synthesizable comparator with standard logic gates. Therefore, circuit calibration techniques such as offset cancellation [21], and majority voting [46], are used for high-resolution applications.

D. System Calibration

The digital background calibration techniques [47], [48], [49], [50], [51], [52], [53], [54], [55], [56], [57], [58] has been incorporated into the digital control logic to improve the signal-to-noise-distortion (SNDR) performance of SAR ADC. During normal operation, background calibration tracks and calibrates in real-time and can be categorized into three categories [47]: (i) Correlation-based techniques involve injecting a pseudorandom noise sequence into the input signal, then removing it afterward [51], [52], [53], [54]. PN sequence is used to calibrate the digital output of SAR ADC by correlating quantization error (the difference between input and quantized output). (ii) Difference-based techniques [47], [48], [49], [50] convert the input signal twice, where the difference between the two residues is used to fine-tune the calibration algorithm. With these two residues highly correlated with quantization error, these techniques require fewer calibration cycles than correlation-based techniques [47]. (iii) Statistical-based techniques use M× comparison after the end of conversion (EOC) to estimate a more accurate quantization of input signals via statistical prediction [55], [56], [57], [58]. Trade-off analysis is presented in Table 3

TABLE 3 Different Types of ADC Calibration Techniques

for these digital calibration techniques. It is most often favored to use statistically-based techniques thanks to their ability to be easily incorporated into most SAR ADC design architectures.

SECTION IV. Conclusion

The comparative analysis of design methodologies for synthesizable SAR ADCs in IoT applications provides a comprehensive overview of their strengths and limitations. By evaluating various circuit implementation techniques, researchers gain valuable insights into the performance of SAR ADCs in different circuit blocks. This comparison highlights the need for further research and innovation to overcome the challenges associated with analog circuits. The conclusions drawn from this study are able to guide our future research directions, stimulating the development of more efficient and cost-effective solutions for SAR ADCs in IoT applications.