I. Introduction
In the modern era of ultra-high-scale integration, the semiconductor industry faces several challenges due to the increasing short-channel effects (SCEs) in nanoscale FET devices. The scaling of CMOS transistors has been continually advancing to achieve high-speed operation and high packing density in modern integrated circuits [1]. As transistor scaling progresses towards smaller technology nodes, several proposed devices aim to meet the performance and scaling requirements of these nodes. Nanosheet [2] - [3], Complementary FET (CFET), and Forksheet [4]–[6] are among the available options.