Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric–Insulator-Si (MFIS) FeFET

In this study, we investigated the impact of unstable and stable interface trap charges ( ${Q}_{\text {it}}\text {)}$ on ${P}_{\text {S}}$ switching in metal-ferroelectric–insulator-Si (MFIS) ferroelectric field-effect transistors (FeFETs), which vary with the thickness of the insulator. We also examine how these variations ultimately affect the various performance metrics of MFIS FeFETs. To achieve this, we varied the thickness of the insulator ( ${t}_{\text {IL}}\text {)}$ in MFIS FeFETs to 1.5, 2.0, and 2.5 nm, thereby controlling the amount of ${Q}_{\text {it}}$ injected from the channel into the ferroelectric (FE)/insulator interface. As ${t}_{\text {IL}}$ decreases, the amount of ${Q}_{\text {it}}$ increases, which amplifies the electric field across the FE layer. As a result, ${P}_{\text {S}}$ switching enhances, and consequently, the MW characteristics of MFIS FeFETs improve. Furthermore, to analyze this in detail, we employed ${P}_{\text {S}}$ – ${Q}_{\text {it}}$ measurements on MFIS FeFETs to simultaneously extract unstable and stable ${Q}_{\text {it}}$ as well as ${P}_{\text {S}}$ and MW. The results show that as ${t}_{\text {IL}}$ increases to 1.5, 2.0, and 2.5 nm, ${Q}_{\text {it}}$ during program/erase (PGM/ERS) operations decreases to 100%, 61%, and 54%, respectively. This leads to a corresponding decrease in ${P}_{\text {S}}$ to 100%, 59%, and 52%. Additionally, after sufficient delay following the PGM/ERS operations, we observe that the proportion stable ${Q}_{\text {it}}$ compared to ${P}_{\text {S}}$ is 91%, regardless to ${t}_{\text {IL}}$ and the remaining 9% of ${P}_{\text {S}}$ contributes to the MW property. Consequently, as ${t}_{\text {IL}}$ increases to 1.5, 2.0, and 2.5 nm, the net charge decreases to 100%, 61%, and 54%, resulting in MW values of 1.85, 1.05, and 0.85 V, respectively. Finally, we analyzed the impact of ${Q}_{\text {it}}$ generation as a function of ${t}_{\text {IL}}$ on the variability and endurance characteristics of MFIS FeFETs.

I. Introduction

Hafnia-based ferroelectric field effect transistors (FeFETs) have recently attracted significant interest as a promising nonvolatile memory (NVM) device for the next generation [1], [2], [3], [4]. This is due to their advantageous features, including compatibility with complementary metal-oxide–semiconductor (CMOS) technology, scalability, and nonvolatility [5], [6], [7]. In particular, FeFETs have become crucial components in neuromorphic computing and in-memory computing applications due to their exceptional reliability, high operational speed, and utilization of multilevel cell (MLC) technology [8], [9], [10]. In addition, FeFETs can be utilized in different configurations, including metal-ferroelectric–insulator-Si (MFIS) structure, metal-ferroelectric–metal-IL–Si (MFMIS) gate stacks with floating metal gate, and metal-IL–ferroelectric-IL–Si (MIFIS) structures that make use of both charge trapping and ferroelectric (FE) switching behavior [11], [12], [13]. The wide range of applications of FeFETs offers limitless possibilities for study.