Positive Interaction Between Charge Trapping and Polarization Switching in Metal-Interlayer-Ferroelectric-Interlayer-Silicon (MIFIS) Ferroelectric Field-Effect Transistor

This study employs analytical simulation to illustrate the beneficial correlation between interface trapped charge and spontaneous polarization ( ${P}_{\text {S}}$ ) switching behavior in the MIFIS gate stack. We found that there is a positive interaction between charge trapping and polarization switching, comprising three sequential processes. 1) In the process of program (erase) operation, electrons (holes) are introduced from the gate metal and are trapped at the interface between the gate interlayer (gate-IL) and the ferroelectric layer. 2) The trapped charge amplifies the electric field across the ferroelectric (FE) layer, subsequently enhancing ${P}_{\text {S}}$ . 3) The increase in ${P}_{\text {S}}$ intensified the induced field on the gate-IL which boosts the charge injection. The three processes are reiterated as previously mentioned. The results indicate that the significant memory window (MW) observed in MIFIS ferroelectric field-effect transistor (FeFET) is a consequence of the combined effect of trapped charges and polarization switching charges, rather than separate contributions. Lastly, with the calibrated simulation model, we provide strategies to improve the device performance in terms of MW and operation speed. The experimental findings and analytic comprehension in this work provide a foundation for future researches on FeFET.

I. Introduction

Today, ferroelectric field-effect transistor (FeFET) has attracted massive attention as a promising candidate for next-generation 3D NAND technology. FeFET is suitable for replacing conventional charge trap-based 3D NAND thanks to its low voltage, high scalability, and CMOS compatibility [1], [2], [3], [4], [5], [6]. However, traditional FeFET featuring a metal-FE-insulator-Si (MFIS) gate stack has a limited MW ( V), hindering the quad-level-cell (QLC) programmability for high-density non-volatile memory (NVM) applications. In MFIS FeFET, the injected charge from the gate compensates that polarization which consequently limits the MW of the FeFET [7], [8]. This narrow MW has hindered the use of FeFET technology in 3D VNAND [9]. To enlarge the MW characteristic of FeFET, the heterostructure (FE/Al₂O₃/FE) FeFET has been proposed to reduce the capacitance of the FE layer (C_FE) while maintaining the optimized thickness of the FE layer for large polarization. It is experimentally verified that MW can be expanded up to 7.1 V without sacrificing the operation speed of the device [10], [11]. However, it still requires further expansion of MW to replace the conventional 3D charge trap flash NAND. Also, the intricate structures of FeFETs with floating gates [12], [13], [14], [15], [16] or double gates [17], [18], [19] render them unsuitable for use with the current 3D vertical NAND mold [20].